Bit 6 Reserved; Transmit Short Packet (Tsp) - Intel IXP45X Developer's Manual

8.5.7.7

Bit 6 Reserved

Bit 6 is reserved for future use.
8.5.7.8

Transmit Short Packet (TSP)

Software uses the transmit short to indicate that the last byte of a data transfer has
been sent to the FIFO. This indicates to the UDC that a short packet or zero-sized
packet is ready to transmit.
Software must not set this bit if a packet of 8 bytes is to be transmitted. When the data
packet is successfully transmitted, the UDC clears this bit.
Register Name:
0x C800B024
Hex Offset Address:
Register
Universal Serial Bus Device Controller Endpoint 5 Control and Status Register
Description:
Access: Read/Write
31
Bits
31:8
7
6
5
4
3
2
1
0
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
306
® ®
Intel IXP45X and Intel
(Reserved)
X
Resets (Above)
Register
Name
Reserved for future use.
Transmit short packet (read/write 1 to set).
TSP
1 = Short packet ready for transmission.
(Reserved). Always reads 0.
Force STALL (read/write).
FST
1 = Issue STALL handshakes to IN tokens
Sent STALL (read/write 1 to clear).
SST
1 = STALL handshake was sent.
Transmit FIFO underrun (read/write 1 to clear).
TUR
1 = Transmit FIFO experienced an underrun.
Flush Tx FIFO (always read 0/ write a 1 to set).
FTF
1 = Flush Contents of TX FIFO.
Transmit packet complete (read/write 1 to clear).
TPC 0 = Error/status bits invalid.
1 = Transmit packet has been sent and error/status bits are valid.
Transmit FIFO service (read-only).
TFS 0 = Transmit FIFO has no room for new data.
1 = Transmit FIFO has room for 1 complete data packet.
IXP46X Product Line of Network Processors—USB 1.1 Device
UDCCS5
0x00000001
Reset Hex Value:
Bits
UDCCS5
Description
Controller
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0
August 2006
Order Number: 306262-004US
0
1