Udc Byte Count Register 14; Endpoint 14 Byte Count (Bc[7:0]); Udc Endpoint 0 Data Register - Intel IXP45X Developer's Manual

USB 1.1 Device Controller—Intel
Processors
Bits
31:8
7:0
8.5.29

UDC Byte Count Register 14

The Byte-Count Register maintains the remaining byte count in the active buffer of out
Endpoint 14.
8.5.29.1

Endpoint 14 Byte Count (BC[7:0])

The byte count is updated after each byte is read. When software receives an interrupt
that indicates the endpoint has data, it can read the byte count register to determine
the number of bytes that remain to be read.
The number of bytes that remain in the input buffer is equal to the byte count +1.
Register Name:
0 x C800B07C
Hex Offset Address:
Register
Universal Serial Bus Device Endpoint 14 Byte Count
Description:
Access: Read-Only
31
Bits
31:8
7:0
8.5.30

UDC Endpoint 0 Data Register

The UDC Endpoint 0 Data Register is an 16-entry by 8-bit bidirectional FIFO. When the
host transmits data to the UDC Endpoint 0, the Intel XScale processor reads the UDC
Endpoint 0 Register to access the data.
When the UDC sends data to the host, the Intel XScale processor writes the data to be
sent in the UDC Endpoint 0 Register. The Intel XScale processor can only read and write
the FIFO at specific points in a control sequence.
August 2006
Order Number: 306262--, Revision: 004US
® ®
IXP45X and Intel IXP46X Product Line of Network
Register
Name
(Reserved)
Byte Count (read-only).
BC
Number of bytes in the FIFO is Byte Count plus 1 (BC+1).
Bits
(Reserved)
X
Resets (Above)
Register
Name
(Reserved)
Byte Count (read-only).
BC
Number of bytes in the FIFO is Byte Count plus 1 (BC+1).
Intel
UBCR12
Description
UBCR14
0x00000000
Reset Hex Value:
UBCR14
Description
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
(UBCR14)
8 7
BC[7:0]
0 0 0 0 0 0 0
(UDDR0)
Developer's Manual
0
0
341