Receive Control 1 - Intel IXP45X Developer's Manual

6.2.9

Receive Control 1

Register Name:
0xC8009010
Hex Offset Address:
Register
Receive Control Register
Description:
Access: Read/Write.
31
Bits
31:8
7
6
5
4
3
2
1
0
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
250
® ®
Intel IXP45X and Intel
(Reserved)
Register
Name
(Reserved)
Broadcast packets will only be dropped if broadcast disable is set to "1", the
address mask register is NOT 00 00 00 00 00 00 and the address filter is
enabled. Setting the address mask register to all 00 (don't care about the
Broadcast
address) and setting the Broadcast disable bit to "1" (checking the address) at
disable
the same time is a contradiction and will result in broadcast packets still being
received and the packet status (MCST_PKT / BCST_PKT) will be read back
accordingly.
1 = Causes runt packets to be passed to the application logic.
Receive runt
packet
0 = Runt packets are dropped.
Address filter 1 = Causes address filtering to take place. Non-broadcast packets are only
enable passed to the application logic if they pass the address filter.
1 = Causes loop-back operation.
Loopback Note: In order for the loop-back operation to operate correctly, the Ethernet
enable coprocessor requires synchronous and in-phase clocks to be provided
on the rx_clk and tx_clk pins.
1 = Enables detection of Pause frames. Upon detecting a pause frame, data
transmission is halted based on the data in the pause frame. The 2-byte data of
Pause enable
the received pause frame indicates the time, as a number of 512 bit times, to
halt the transmission.
Send CRC 1 = Causes the CRC data to be sent to the application logic.
Pad strip 1 = Causes the pad bytes to be stripped from receive data.
Receive
1 = Causes reception to be enabled.
enable
IXP46X Product Line of Network Processors—Ethernet MACs
rxctrl1
0x00000000
Reset Hex Value:
rxcrtl1
Description
8 7 6 5 4 3 2 1
August 2006
Order Number: 306262-004US
0