Intel IXP45X Developer's Manual page 25

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Contents-Intel IXP45X and Intel
27.6.5 Queues 32-63 Nearly Empty Status Register ............................................ 941
27.6.6 Queues 32-63 Nearly Full Status Register ................................................ 942
27.6.7 Queues 32-63 Full Status Register .......................................................... 942
27.6.8 Interrupt 0 Status Flag Source Select Register 0 - 3 ................................. 942
27.6.9 Queue Interrupt Enable Register 0 - 1 .................................................... 944
27.6.10Queue Interrupt Register 0 - 1 .............................................................. 944
27.6.11Queue Configuration Words 0 - 63 .......................................................... 945
27.6.12Queue 32 to 63 Event 'A' Enable Register ................................................ 946
27.6.13Queue 32 to 63 Event 'B' Enable Register ................................................ 946
27.6.14Queue 32 to 63 Event 'C' Enable Register ................................................ 946
27.6.15Event Source Select.............................................................................. 947
27.6.16Queue 0 to 31 Status Selection Map Register ........................................... 948
27.6.17Queue SRAM Error Data Register ............................................................ 949
27.6.18Queue SRAM Error Address/Control Register ............................................ 949
27.7 Error/Abnormal Conditions ............................................................................... 949
28.0 Error Handling ....................................................................................................... 951
28.1 Errors ............................................................................................................ 951
28.1.1 Sources of AHB Bus Errors..................................................................... 951
28.1.1.1 Accesses to Reserved or Unimplemented Addresses..................... 951
28.1.1.2 Illegal-Access Types ................................................................ 951
28.1.1.3 Expansion Bus Parity Error ....................................................... 951
28.1.1.4 AQM-Parity Error .................................................................... 951
28.1.1.5 Memory Controller Unit (MCU), Multiple-Bit, ECC Error ................. 951
28.2 Responses to Errors......................................................................................... 952
28.2.1 PCI Responses to Errors ........................................................................ 952
28.2.2 NPE Responses to Errors ....................................................................... 952
28.2.3 Expansion Bus Controller Response to Errors............................................ 957
28.2.4 Intel XScale
28.2.5 AHB-AHB Bridge Response to Errors ....................................................... 957
28.3 Multiple Error Conditions .................................................................................. 957
Figures
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1 Intel IXP465 Network Processor Block Diagram .......................................................... 45
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2 Intel IXP460 Network Processor Block Diagram .......................................................... 46
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3 Intel IXP455 Network Processor Block Diagram .......................................................... 47
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4 Intel XScale Processor Block Diagram ....................................................................... 62
5 Example of Locked Entries in TLB ............................................................................... 77
6 Instruction Cache Organization .................................................................................. 78
7 Locked Line Effect on Round-Robin Replacement .......................................................... 82
8 BTB Entry ............................................................................................................... 84
9 Branch History......................................................................................................... 84
10 Data Cache Organization........................................................................................... 86
11 Mini-Data Cache Organization .................................................................................... 87
12 Locked Line Effect on Round-Robin Replacement .......................................................... 95
13 SELDCSR Hardware ................................................................................................ 125
14 SELDCSR Data Register .......................................................................................... 126
15 DBGTX Hardware ................................................................................................... 128
16 DBGRX Hardware ................................................................................................... 129
17 Rx Write Logic ....................................................................................................... 130
18 DBGRX Data Register ............................................................................................. 131
19 Message Byte Formats ............................................................................................ 134
20 Indirect Branch Entry Address Byte Organization ........................................................ 137
21 High-Level View of Trace Buffer ............................................................................... 137
August 2006
Order Number: 306262-004US
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IXP46X Product Line of Network Processors
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Processor Response to Errors ............................................. 957
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Intel
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IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
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