Intel IXP45X Developer's Manual page 15

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Contents-Intel IXP45X and Intel
9.15.4.3 Port Test Mode ....................................................................... 492
9.16 Compatibility .................................................................................................. 493
9.17 Power-Management Requirements..................................................................... 493
9.17.1 USB Power States ................................................................................ 493
9.17.2 Host Power States ................................................................................ 493
9.18 Error/Abnormal Conditions ............................................................................... 493
10.0 PCI Controller ........................................................................................................ 495
10.1 Introduction ................................................................................................... 495
10.2 Overview ....................................................................................................... 495
10.2.1 List of Features .................................................................................... 500
10.2.2 PCI Controller Configured as Host ........................................................... 501
10.2.2.1 Example: Generating a PCI Configuration Write and Read ............ 503
10.2.3 PCI Controller Configured as Option ........................................................ 504
10.2.4 Initializing PCI Controller Configuration and Status Registers
for Data Transactions............................................................................ 505
10.2.4.1 Example: AHB Memory Base Address Register, AHB I/O Base
10.2.4.2 Example: PCI Memory Base Address Register and
10.2.5 Initializing the PCI Controller Configuration Registers ................................ 509
10.2.6 PCI Controller South AHB Transactions .................................................... 512
10.2.7 PCI Controller Functioning as Bus Initiator ............................................... 512
10.2.7.1 Initiated Type-0 Read Transaction ............................................. 513
10.2.7.2 Initiated Type-0 Write Transaction ............................................ 513
10.2.7.3 Initiated Type-1 Read Transaction ............................................. 514
10.2.7.4 Initiated Type-1 Write Transaction ............................................ 515
10.2.7.5 Initiated Memory Read Transaction ........................................... 516
10.2.7.6 Initiated Memory Write Transaction ........................................... 517
10.2.7.7 Initiated I/O Read Transaction .................................................. 517
10.2.7.8 Initiated I/O Write Transaction ................................................. 518
10.2.7.9 Initiated Burst Memory Read Transaction ................................... 519
10.2.7.10Initiated Burst Memory Write Transaction................................... 520
10.2.8 PCI Controller Functioning as Bus Target ................................................. 521
10.2.9 PCI Controller Door Bell Register ............................................................ 521
10.3 Functional Description...................................................................................... 522
10.3.1 PCI Byte-Enable Generation................................................................... 522
10.3.2 PCI Core ............................................................................................. 522
10.3.2.1 PCI Target Interface................................................................ 523
10.3.2.2 PCI Initiator Interface.............................................................. 524
10.3.2.3 PCI Host Functions.................................................................. 526
10.3.2.4 PCI Controller Clock and Reset Generation ................................. 528
10.3.2.5 PCI Configuration Register Access ............................................. 528
10.3.2.6 PCI Pad Drive Strength Compensation Support ........................... 529
10.3.2.7 AHB Master Interface .............................................................. 530
10.3.2.8 AHB Master Writes .................................................................. 531
10.3.2.9 AHB Master Reads .................................................................. 532
10.3.2.10AHB Slave Interface ................................................................ 532
10.3.2.11PCI Byte Enable Generation...................................................... 535
10.3.3 PCI Controller DMA............................................................................... 536
10.3.3.1 AHB-to-PCI DMA Channel Operation .......................................... 540
10.3.3.2 PCI-to-AHB DMA Channel Operation .......................................... 540
10.3.4 Data Byte Alignment and Addressing - PCI Endianness............................. 541
10.3.5 PCI Controller Interrupts ....................................................................... 547
10.3.5.1 PCI Interrupt Generation ......................................................... 547
10.3.5.2 Internal Interrupt Generation ................................................... 548
10.4 PCI RCOMP Circuitry ........................................................................................ 549
August 2006
Order Number: 306262-004US
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IXP46X Product Line of Network Processors
Address Register, and PCI Memory Base Address Register ............ 507
South-AHB Translation ............................................................ 508
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Intel
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IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
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