Intel IXP45X Developer's Manual page 462

Intel
As with asynchronous Full- and Low-speed endpoints, a split-transaction state machine
is used to manage the split transaction sequence. Aside from the fields defined in the
queue head for scheduling and tracking the split transaction, the host controller
calculates one internal mechanism that is also used to manage the split transaction.
The internal calculated mechanism is:
• cMicroFrameBit. This is a single-bit encoding of the current micro-frame number. It
is an eight-bit value calculated by the host controller at the beginning of every
micro-frame. It is calculated from the three least significant bits of the FRINDEX
register (i.e. cMicroFrameBit = (1 shifted-left(FRINDEX[2:0]))). The
cMicroFrameBit has at most one bit asserted, which always corresponds to the
current micro-frame number. For example, if the current micro-frame is 0, then
cMicroFrameBit will equal 00000001b.
The variable cMicroFrameBit is used to compare against the S-mask and C-mask fields
to determine whether the queue head is marked for a start- or complete-split
transaction for the current micro-frame.
Figure 71
transaction. There are two phases to each split transaction. The first is a single start-
split transaction, which occurs when the SplitXState is at Do_Start and the single bit in
cMicroFrameBit has a corresponding bit active in QH.S-mask. The transaction translator
does not acknowledge the receipt of the periodic start-split, so the host controller
unconditionally transitions the state to Do_Complete. Due to the available jitter in the
transaction translator pipeline, there will be more than one complete-split transaction
scheduled by software for the Do_Complete state. This translates simply to the fact
that there are multiple bits set to a one in the QH.C-mask field.
The host controller keeps the queue head in the Do_Complete state until the split
transaction is complete (see definition below), or an error condition triggers the three-
strikes-rule (e.g. after the host tries the same transaction three times, and each
encounters an error, the host controller will stop retrying the bus transaction and halt
the endpoint, thus requiring system software to detect the condition and perform
system-dependent recovery).
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
462
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller
illustrates the state machine for managing a complete interrupt split
August 2006
Order Number: 306262-004US