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19.5.2.2
Time Sync Event Register
Register Name:
Block
RegBlockAddress
Base Address:
Time Sync Event Register
Register Description:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Register
Bits
Name
31:4
(Reserved)
Reserved for future use.
AMMS Snapshot. This event bit sets when the system time register value is
captured in the Auxiliary Master Mode Snapshot register upon an active high
level on a general-purpose input, ammssig.
3
snm
• When this signal is asserted high, an interrupt will be generated to the
• To clear snm, write a '1' to it.
ASMS Snapshot. This event bit sets when the system time register value is
captured in the Auxiliary Slave Mode Snapshot register upon detection of an
active high level on a general-purpose input, asmssig.
2
sns
• When this signal is asserted high, an interrupt will be generated to the
• To clear the sns bit, write a '1' to it.
Target Time Interrupt Pending. This bit is the Target Time interrupt
pending indication. When this bit is set, it indicates that the Target Time
interrupt condition has occurred, which means that the System Time value has
reached the 64-bit Target Time register value.
• If ttm in the Time Sync Control register is set, the interrupt will be passed
1
ttipend
• To clear this condition, the firmware must write a '1' to the ttipend bit.
To prevent an immediate reoccurrence of the target time interrupt, the
processor should first write a new value to the Target Time register and then
clear the condition. This bit is set at power-up since both the System Time and
the Target Time are reset at power-up to 0.
0
(Reserved)
Reserved for future use.
Addend Register
19.5.2.3
Register Name:
Block
RegBlockAddress
Base Address:
Time Sync Addend Register
Register Description:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
®
®
Intel
IXP45X and Intel
IXP46X Product Line of Network Processors
Developer's Manual
840
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors—Time Synchronization
Offset Address
(Reserved)
Description
Host on the ts_intreq if the amm bit in the Time Sync Control register is
also set.
Host on the shared interrupt signal (ts_ntreq) if the asm bit in the Time
Sync Control register is set.
to the Host processor.
Offset Address
Addend[31:0]
TS_Event
0x004
Reset Value
8
7
TS_Event
TS_Addend
0x008
Reset Value
8
7
Order Number: 306262-004US
Hardware Assist (TSYNC)
x0010
Access:
(See below.)
6
5
4
3
2
1
0
Reset
Access
Value
x
x
0
RW
0
RW
1
RW
0
RW
0x0
Access:
(See below.)
6
5
4
3
2
1
0
August 2006
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