Initiated Pci I/O Read Cycle; Initiated I/O Write Transaction - Intel IXP45X Developer's Manual

Figure 86.

Initiated PCI I/O Read Cycle

PCI_CLK
INT_REQ_N
INT_GNT_N
PCI_FRAME_N
PCI_AD (31:0)
PCI_IDSEL
PCI_CBE_N
PCI_IRDY_N
PCI_TRDY_N
PCI_DEVSEL_N
10.2.7.8

Initiated I/O Write Transaction

The following transaction is a PCI I/O Write Cycle initiated from the IXP45X/IXP46X
network processors. This diagram is to understand the inner workings of PCI transfers
and may not reflect actual operation of the PCI Controller implemented on the IXP45X/
IXP46X network processors. The transaction is initiated to address location
hexadecimal 0x00000015. The value of binary 01 in PCI_AD (1:0) indicates that the
transfer is a valid byte address of the first byte of 32-bit word address 0x00000014
(0x00000014 + 0x00000001 = 0x00000015).
The byte-enables being 0xD — during the data transfer — signify that the transfer is a
byte transfer to the above-mentioned address. A hexadecimal value of 0x3 written on
the PCI_CBE_N bus during the address phase signifies that this is a PCI Bus I/O Write
Cycle.
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
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August 2006
Order Number: 306262-004US