Theory Of Operation - Intel IXP45X Developer's Manual

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GPIO Controller—Intel IXP45X and Intel
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Figure 185. GPIO Block Diagram
GPIO
Pin
15.4

Theory of Operation

The GPIO pin is controlled through six registers and two more registers provide status.
Each register can be read through the APB interface and all registers except GPINR can
be written through the APB interface.
The GPIO on the IXP45X/IXP46X network processors can be configured to be used as
general-purpose inputs or general-purpose outputs. Three 16-bit registers are used in
order to configure, initialize, and use the general-purpose I/O. These registers are:
• General-Purpose Data Output Register (GPOUTR)
• General-Purpose Output Enable Register (GPOER)
• General-Purpose Input Status Register (GPINR)
The General-Purpose Output Enable Register is used to configure the GPIO pins as an
input or an output. There is a one-for-one relationship between the register bit
mapping and the GPIO. For example, bit 0 of the general-purpose Output Enable
Register corresponds to GPIO 0 and bit 1 of the General-Purpose Output Enable
Register corresponds to GPIO 1.
When a bit of the General-Purpose Enable Register contains logic 0, the corresponding
GPIO will be configured as an output. A logic 1 in the same bit of the General-Purpose
Enable Register will cause the corresponding GPIO to be configured as an input.
For example, the General-Purpose Output Enable Register contains a hexadecimal
value of 0x00000500. GPIO 8 and GPIO 10 will be configured as inputs and all other
GPIO will be configured as outputs. The GPIO that are configured as outputs — by the
values contained in the General-Purpose Enable Register — will be driven by the values
contained in the General-Purpose Data Output Register.
The General-Purpose Data Output Register is a 16-bit register with a one-for-one
correspondence between the 16 bits of the General-Purpose Data Output Register and
the 16-bit GPIO. When logic 1 is written to a bit in the General-Purpose Data Output
Register — and the corresponding bit in the General-Purpose Enable Register is set to
logic 0 — logic 1 will be replicated to the corresponding GPIO. When logic 0 is written to
August 2006
Reference Number: 306262-004US
®
IXP46X Product Line of Network Processors
CLK GEN
Wave Shape
®
Intel IXP45X and Intel
GPOER
GPDBSELR
GPOUTR
GPCLKR
APB
GPINR
Interface
GPIO_INTR
GPISR
GPIT1R
GPIT2R
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IXP46X Product Line of Network Processors
GPIO_INT_NPE
B4231-01
Developer's Manual
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