Frindex - Intel IXP45X Developer's Manual

Intel
Table 136. USBINTR – USB Interrupt Enable
Field
FRE
PCE
UEE
UE
9.12.4

FRINDEX

Address:
Default Value: Undefined (free running counter)
Attribute:
Size:
This register is used by the host controller to index the periodic frame list. The register
updates every 125 ms (once each micro-frame). Bits [N: 3] are used to select a
particular entry in the Periodic Frame List during periodic schedule execution. The
number of bits used for the index depends on the size of the frame list as set by system
software in the Frame List Size field in the USBCMD register.
This register must be written as a DWord. Byte writes produce-undefined results. This
register cannot be written unless the Host Controller is in the 'Halted' state as indicated
by the HCHalted bit. A write to this register while the Run/Stop hit is set to a one
produces undefined results. Writes to this register also affect the SOF value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
378
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IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller
Interrupt
Source
When this bit is a one, and the Frame List Rollover bit in the USBSTS
register is a one, the host controller will issue an interrupt. The
Frame List
interrupt is acknowledged by software clearing the Frame List Rollover
Rollover
bit.
Enable
Only used by the host controller.
When this bit is a one, and the Port Change Detect bit in the USBSTS
Port Change register is a one, the host controller will issue an interrupt. The
Detect Enable interrupt is acknowledged by software clearing the Port Change Detect
bit.
When this bit is a one, and the USBERRINT bit in the USBSTS register
USB Error
is a one, the host controller will issue an interrupt at the next interrupt
Interrupt
threshold. The interrupt is acknowledged by software clearing the
Enable
USBERRINT bit in the USBSTS register.
When this bit is a one, and the USBINT bit in the USBSTS register is a
USB Interrupt one, the host controller will issue an interrupt at the next interrupt
Enable threshold. The interrupt is acknowledged by software clearing the
USBINT bit.
Base + 14Ch
Read/Write in host mode
32 bits
(Reserved)
Description
8 7 6 5
FRINDEX[13:0]
Order Number: 306262-004US
4 3 2 1 0
August 2006