Dual Port Ram Controller; Protocol Engine; Protocol Engine Block Diagram - Intel IXP45X Developer's Manual

USB 2.0 Host Controller—Intel
9.6.3.4

Dual Port RAM Controller

The Dual Port RAM Controller is used for context information and to build
configurable FIFOs between the Protocol Engine block and the DMA controller. These
FIFOs decouple the system processor memory bus request from the extremely tight
timing required by the USB itself.
9.6.3.5

Protocol Engine

Figure 43.

Protocol Engine Block Diagram

The Protocol Engine parses all the USB tokens and generates the response packets. It
is responsible for all error checking, check field generation, formatting all the
handshake, ping and data response packets on the bus, and for any signals that must
be generated based on a USB based time frame. In host mode, the Protocol engine also
generates all of the token packets required by the USB protocol. The Protocol engine
contains several sub-functions:
• The token state machines track all of the tokens on the bus and filter the traffic
based on the address and endpoint information in the token. In host mode, these
state machines also generate the tokens required for data transfer and bus control.
August 2006
Order Number: 306262--, Revision: 004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
To Microprocessor Interface
To DMA (Prime Bus)
Vusb_hs_pe_
datapath
Muxing/
TX FIFO
Pipelining
FIFO
Control
RX FIFO
CRC
Port Controller
Interface
To DMA (Packet/SOF Control)
Vusb_hs_pe_
dev_sm
Prime Logic
PID
Tracking
Handshake
Decision
Logic
Datapath
Control
Vusb_hs_pe_
hst_sm
SOF
Generation
PID
Generation
Handshake
Decision
Logic
Datapath
Control
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Vusb_hs_pe
_timers
Bus
Timeout
Inter-Packet
Delay
Vusb_hs_pe_
timebase
Generate
Frame/
MicroFrame
and Scheduler
Timing
strobes
B4204-01
Developer's Manual
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