Ddri Sdram Pipelined Reads; Ddri Sdram Read Cycle - Intel IXP45X Developer's Manual

11.2.2.10

DDRI SDRAM Read Cycle

The MCU performance is optimized for page hits and the MCUs behavior is different for
the hit and miss scenario.
The waveform for a read including the row activation in the case of a page miss is
illustrated in
saved resulting in lower first word read latency.
The MCU supports optimized performance for random address transactions. This
optimization eliminates the need of the DDRI SDRAM Control Block to issue the
transaction command to the DDRI array if the previous transaction is the same type
(read or write). In addition, the DDRI SDRAM Control Block supports pipelining of
transactions which allows the column address of the next transaction to be issued
before the current transaction's data transfer is completed by the DDRI SDRAM
devices. These optimizations are illustrated in
transactions.
Figure 113. DDRI SDRAM Pipelined Reads
CK_N
Command
Address
DQS
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
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Intel IXP45X and Intel
Figure 114. For a page hit, the two cycles required for row activation are
CK
Read Read
Bank Col n Bank Col x
CL = 2
DQ
IXP46X Product Line of Network Processors—Memory Controller
Figure 113
Read Read
Bank Col b Bank Col g
Do n Do n'
for random read memory
NOP NOP
Do x Do x' Do b Do b'
Order Number: 306262-004US
Do g
B0406-02
August 2006