Rx Write Logic - Intel IXP45X Developer's Manual

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and sets DBG_REG[34] to signal the data is valid. Since DBG_REG[34] is never
cleared by the debugger in this case, the '0' to '1' transition used to enable the
debugger write to RX would not occur.
• Set TXRXCTRL[31] - When the debugger writes new data to RX, the logic
automatically sets TXRXCTRL[31], signalling to the debug handler that the data is
valid.
• Set the overflow flag (TXRXCTRL[30] - During high-speed download, the debugger
does not poll to see if the handler has read the previous data. If the debug handler
stalls long enough, the debugger may overwrite the previous data before the
handler can read it. The logic sets the overflow flag when the previous data has not
been read yet, and the debugger has just written new data to RX.
Figure 17.

Rx Write Logic

3.6.11.6.2 DBGRX Data Register
The bits in the DBGRX data register
to the processor. The data register also contains a bit to flush previously written data
and a high-speed download flag.
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
130
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IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale
DBG_REG[34]
TXRXCTRL[31]
Core CLK
Clear DBG_REG[34]
RX write enable
set TXRXCTRL[31]
(Figure 18) are used by the debugger to send data
®
Processor
set overflow flag
(TXRXCTRL[30])
B4343-01
August 2006
Order Number: 306262-004US