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Sharing resources among different applications requires a state saving mechanism.
Two possibilities are:
• The operating system, during a context switch, could save the state of the
coprocessor if the last executing process had access rights to the coprocessor.
• The operating system, during a request for access, saves off the old coprocessor
state and saves it with last process to have access to it.
Under both scenarios, the OS needs to restore state when a request for access is made.
This means the OS has to maintain a list of what processes are modifying CP0 and their
associated state.
Example 12. Disallowing access to CP0
;; The following code clears bit 0 of the CPAR.
;; This will cause the processor to fault if software
;; attempts to access CP0.
Table 28.
Coprocessor Access Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: 0x0000,0000
Bits
31:16
15:14
13:1
0
3.5.2
CP14 Registers
Table 29
®
®
Intel
IXP45X and Intel
IXP46X Product Line of Network Processors
Developer's Manual
108
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors—Intel XScale
LDR R0, =0x3FFE
MCR P15, 0, R0, C15, C1, 0
CPWAIT
Access
Read-unpredictable / Write-as-Zero
Read-as-Zero/Write-as-Zero
Read / Write
Read / Write
lists the CP14 registers implemented in the Intel XScale processor.
; bit 0 is clear
; move to CPAR
; wait for effect
8
C
C
C
C
C
C
P
P
P
P
0 0
P
P
1
1
1
1
9
8
3
2
1
0
Description
Reserved - Should be programmed to zero for future
compatibility
Reserved - Should be programmed to zero for future
compatibility
Coprocessor Access Rights-
Each bit in this field corresponds to the access rights for
each coprocessor.
Coprocessor Access Rights-
This bit corresponds to the access rights for CP0.
0 = Access denied. Any attempt to access the
corresponding coprocessor will generate an
undefined exception.
1 = Access allowed. Includes read and write accesses.
Order Number: 306262-004US
®
Processor
7
6
5
4
3
2
1
0
C
C
C
C
C
C
C
C
P
P
P
P
P
P
P
P
7
6
5
4
3
2
1
0
August 2006
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