Performance Considerations; Interrupt Latency - Intel IXP45X Developer's Manual

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Intel XScale Processor—Intel
Example 19. Speculatively issuing PLD
;; R0 points to a node in a linked list. A node has the following layout:
;; Offset Contents
;;----------------------------------
;; 0 data
;; 4 pointer to next node
;; This code computes the sum of all nodes in a list. The sum is placed into R9.
;;
MOV R9, #0
sumList:
LDR R1, [R0, #4]
LDR R3, [R0]
PLD [R1]
ADD R9, R9, R3
MOVS R0, R1
BNE sumList
3.8.3.4.6 Debug Events
Debug events are covered in
3.9

Performance Considerations

This section describes relevant performance considerations that compiler writers,
application programmers, and system designers need to be aware of to efficiently use
the IXP45X/IXP46X network processors. Performance numbers discussed here include
interrupt latency, branch prediction, and instruction latencies.
3.9.1

Interrupt Latency

Minimum Interrupt Latency is defined as the minimum number of cycles from the
assertion of any interrupt signal (IRQ or FIQ) to the execution of the instruction at the
vector for that interrupt. This number assumes best case conditions exist when the
interrupt is asserted, e.g., the system isn't waiting on the completion of some other
operation.
A sometimes more useful number to work with is the Maximum Interrupt Latency. This
is typically a complex calculation that depends on what else is going on in the system
at the time the interrupt is asserted. Some examples that can adversely affect interrupt
latency are:
• The instruction currently executing could be a 16-register LDM
• The processor could fault just when the interrupt arrives
• The processor could be waiting for data from a load, doing a page table walk, etc.
• High core-to-system (bus) clock ratios
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
; Clear accumulator
; R1 gets pointer to next node
; R3 gets data from current node
; Speculatively start load of next node
; Add into accumulator
; Advance to next node. At end of list?
; If not then loop
"Debug Exceptions" on page
Intel
115.
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
181