Internal Buses - Intel IXP45X Developer's Manual

5.0

Internal Buses

The internal bus architecture of the Intel
Network Processors is designed to allow parallel processing to occur and isolate bus
utilization based upon particular traffic patterns. The bus is segmented into four major
buses, MPI, the North AHB, the South AHB, and the APB.
The Memory Port Interface provides a dedicated interface between the Intel XScale
Processor and the DDRI SDRAM. This interface is a 133-MHz, 64-bit bus that is
mastered by the Intel XScale processor only. The only target of this interface is the
DDRI SDRAM controller.
By providing a dedicated path which supports multiple outstanding queues, split, and
posted transactions, this interface can achieve better memory performance over
previous generation products. Isolation of the interface also allows more DDRI SDRAM
performance to be allocated to the Intel XScale processor.
The North AHB is a 133-MHz, 32-bit bus that can be mastered by the NPE A Network
Processor Engine (NPE), NPE B, or NPE C. The targets of the North AHB can be the
DDRI SDRAM controller or the AHB/AHB Bridge. The AHB/AHB Bridge will allow access
by the NPEs to the peripherals and internal targets on the South AHB.
Data transfers by the NPEs from the North AHB to the South AHB are targeted
predominately to the queue manager. Transfers to the AHB/AHB Bridge may be
"posted" when writing or "split" when reading — allowing control of the North AHB to
be given to another master on the North AHB and allowing the bus to achieve
maximum efficiency.
Transfers to the AHB/AHB Bridge are considered to be small and infrequent, relative to
the traffic passed between the NPEs on the North AHB and the DDRI SDRAM.
The South AHB is a 133-MHz, 32-bit bus that can be mastered by the Intel XScale
processor, PCI Controller, Expansion Bus Controller, USB Host 2.0, and the AHB/AHB
Bridge. The targets of the South AHB can be the DDRI SDRAM, PCI Controller, Queue
Manager, Expansion Bus Controller, USB Host 2.0, Cryptography Unit, or the AHB/APB
Bridge. Accessing across the AHB/APB Bridge allows interfacing to peripherals attached
to the APB Bus.
The APB is a 66.66 MHz, 32-bit bus that can be mastered by the AHB/APB Bridge only.
The targets of the APB can be the High-Speed UART Interface, Console UART Interface,
USB 1.1 interface, all NPEs, the Internal Bus Performance Monitoring Unit (PMU),
Interrupt Controller, GPIO, IEEE 1588 hardware assist unit, SSP, I
APB interface to the NPEs is used for NPE code download, part configuration, and status
collection.
The maximum length that any AHB master can hold the AHB is for eight 32-bit words.
This feature allows for fairness among all masters on the AHBs.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
224
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors—Internal Buses
®
IXP45X and Intel
®
IXP46X Product Line of
2
C, and Timers. The
August 2006
Order Number: 306262-004US
®