Timing And Control Registers For Chip Select 6; Timing And Control Registers For Chip Select 7; Bit Level Definition For Each Of The Timing And Control Registers - Intel IXP45X Developer's Manual

Expansion Bus Controller—Intel
Processors
12.5.7

Timing and Control Registers for Chip Select 6

Register Name:
0XC4000018
Hex Offset Address:
Register
Timing and Control Registers
Description:
Access: Read/Write.
31 30 29 28 27 26 25
T1 T2
12.5.8

Timing and Control Registers for Chip Select 7

Register Name:
0XC400001C
Hex Offset Address:
Register
Timing and Control Registers
Description:
Access: Read/Write.
31 30 29 28 27 26 25
T1 T2
Table 228. Bit Level Definition for each of the Timing and Control Registers (Sheet 1 of 2)
Bits
31
30
29:28
27:26
25:22
21:20
19:16
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network
22 21 20 19
T3 T4 T5
22 21 20 19
T3 T4 T5
Name
CSx_EN
PAR_EN
T1 – Address timing
T2 – Setup / Chip Select
Timing
T3 – Strobe Timing
T4 – Hold Timing
T5 – Recovery Timing
EXP_TIMING_CS6
Reset Hex Value:
0x00000000
16 15 14 13
CNFG[4:0]
EXP_TIMING_CS7
Reset Hex Value:
0x00000000
16 15 14 13
CNFG[4:0]
Description
0 = Chip Select x disabled
1 = Chip Select x enabled
0 = Parity is not generated or compared
1 = Parity is generated and compared
Parity is only supported for Intel, Motorola, and Micron ZBT
modes.
00 = Generate normal address phase timing
01 - 11 = Extend address phase by 1 - 3 clocks
00 = Generate normal setup phase timing
01 - 11 = Extend setup phase by 1 - 3 clocks
0000 = Generate normal strobe phase timing
0001-1111 = Extend strobe phase by 1 - 15 clocks
00 = Generate normal hold phase timing
01 - 11 = Extend hold phase by 1 - 3 clocks
0000 = Generate normal recovery phase timing
0001-1111 = Extend recovery phase by 1 - 15 clocks
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
CS6:
9 8 7 6 5 4 3 2
CS7:
9 8 7 6 5 4 3 2
Developer's Manual
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