Intel IXP45X Developer's Manual page 33

®
Contents-Intel IXP45X and Intel
190 PCI Initiator Interface Supported Commands ............................................................. 499
191 PCI Memory Map Allocation ..................................................................................... 508
192 PCI Byte Enables Using CRP Access Method ............................................................... 511
193 PCI Configuration Space.......................................................................................... 511
194 Command Type for PCI Controller Configuration and Status Register Accesses ............... 512
195 PCI Target Interface Supported Commands ............................................................... 523
196 PCI Initiator Interface Supported Commands ............................................................. 525
197 PCI CLOCK and RESET Sourcing ............................................................................... 528
198 PCI Byte Enables for Sub-word Single AHB Read/write Cycles ...................................... 536
199 Register Legend..................................................................................................... 549
200 PCI Configuration Register Map ................................................................................ 550
201 CSR Address Map................................................................................................... 558
202 DDRI SDRAM Memory Configuration Options.............................................................. 588
203 Supported DDRI SDRAM Configurations .................................................................... 590
204 DDRI SDRAM Address Register Summary .................................................................. 591
205 Address Decoding for DDRI SDRAM Memory Banks ..................................................... 591
206 Programming Codes for the DDRI SDRAM Bank Size ................................................... 591
207 Programming Values for the DDRI SDRAM 32-bit Size Register (S32SR[29:20])*............ 592
208 DDRI SDRAM Address Translation for 128/512 Mbit (x16/x8), 1 Gbitx8,
and 256 Mbitx8 Devices .......................................................................................... 593
209 DDRI SDRAM Address Translation for 256 Mbitx16 Devices .......................................... 593
210 DDRI SDRAM Address Translation for 1 Gbitx16 Devices.............................................. 594
211 DDRI SDRAM Commands ........................................................................................ 598
212 Typical Refresh Frequency Register Values ................................................................ 614
213 Syndrome Decoding ............................................................................................... 620
214 MCU Error Response............................................................................................... 627
215 Register Legend..................................................................................................... 630
216 Memory Controller Register Table............................................................................. 630
217 Example Expansion Bus Pin Mappings to Target Devices .............................................. 651
218 Supported AHB Commands...................................................................................... 652
219 Trimmed Version of IXP45X/IXP46X network processors Memory Map ........................... 653
220 Expansion Bus Address and Data Byte Steering.......................................................... 656
221 Multiplexed Output Pins for HPI Operation ................................................................. 664
222 HPI HCNTL Control Signal Decoding.......................................................................... 665
223 Supported Inbound Expansion Bus Transfers ............................................................. 682
224 EX_ADDR Operation ............................................................................................... 685
225 Register Legend..................................................................................................... 701
226 Legacy Expansion Bus Register Summary.................................................................. 702
227 Non-Legacy Expansion Bus Register Summary ........................................................... 702
228 Bit Level Definition for each of the Timing and Control Registers................................... 705
229 Configuration Register 0 Description ......................................................................... 707
230 Setting The Intel XScale
231 Expansion Bus Configuration Register 1-Bit Definition ................................................. 710
232 UTOPIA/Ethernet Configuration Options .................................................................... 715
233 NPE-B Ethernet Configuration Options....................................................................... 715
234 NPE-C Ethernet Configuration Options....................................................................... 715
235 EX_ADDR Value to Access EXP_INBOUND_ADDR Register............................................ 719
236 EX_ADDR Value to Access EXP_LOCK0 Register.......................................................... 720
237 EX_ADDR Value to Access EXP_LOCK1 Register.......................................................... 721
238 HSS Tx/Rx Clock Output ......................................................................................... 735
239 HSS Tx/Rx Clock Output Frequencies and PPM Error ................................................... 735
240 HSS Tx/Rx Clock Output Frequencies and Associated Jitter Characterization................... 735
241 HSS Frame Output Characterization.......................................................................... 736
242 Jitter Definitions .................................................................................................... 736
243 Timeslot Configurations .......................................................................................... 741
August 2006
Order Number: 306262-004US
®
IXP46X Product Line of Network Processors
®
Processor Operation Speed ................................................. 709
®
Intel
®
IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
33