Pci Controller Configuration Port Address/Command/Byte; Enables Register - Intel IXP45X Developer's Manual

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PCI Controller—Intel IXP45X and Intel
10.5.3.5

PCI Controller Configuration Port Address/Command/Byte

Enables Register

Register Name:
Block
0xC00000
Base Address:
PCI configuration port address/command/byte enables register.
Provides address, command, and data byte enables for CSR-
initiated accesses of the PCI Controller PCI configuration registers
in the PCI Core. A write to this register that sets the CRP_CMD[16]
Register Description:
bit to a 0 (read) will initiate a read of the PCI Controller PCI config-
uration register addressed by CRP_AD[7:2]. The resultant read
data will be written to the pci_crp_rdata register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
(Reserved)
Register
Bits Name
31:2
reserved reserved – read as 0
4
Active-low byte enables for a PCI configuration port write access. This field
corresponds to byte lanes in the pci_crp_wdata register and addressed
PCI configuration register as follows:
23:2
CRP_BE[0] −> bits 7:0
CRP_BE
0
CRP_BE[1] −> bits 15:8
CRP_BE[2] −> bits 23:16
CRP_BE[3] −> bits 31:24
Command for the PCI configuration port access.
19:1
CRP_CMD
6
xxx0 = read, xxx1 = write
15:1
reserved reserved – read as 0
1
Byte address for the PCI configuration port access. PCI configuration
10:0 CRP_AD registers are word-addressed so bits 1 and 0 should always be 0. Bits 10:8
specify the function number and must always be 000.
August 2006
Order Number: 306262-004US
®
IXP46X Product Line of Network Processors
Offset Address
CRP_BE CRP_CMD
Description
Intel
pci_crp_ad_cbe
0x10
(Reserved)
pci_crp_ad_cbe
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
0x00000000
Reset Value
Access: (See below.)
8 7 6 5 4 3 2 1
CRP_AD
Reset PCI AHB
Value Access Access
0x00 none
0x0 none
0x0 none
00000 none
0x000 None
Develepor's Manual
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