Ixp455 Network Processor Block Diagram - Intel IXP45X Developer's Manual

Functional Overview—Intel
®
Figure 3. Intel

IXP455 Network Processor Block Diagram

HSS 0
HSS 1
UTOPIA 2/MII/SMII
MII/SMII
MII/SMII
2
I C
SSP
USB Device
Version 1.1
UART 0
921 KBaud
UART 1
921 KBaud
16 GPIO
GPIO
Interrupt
Controller
IBPMU
Timers
Slave Only
Master on South AHB
August 2006
Reference Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
NPE A
NPE B
NPE C
AES/DES/SHA/
MD-5
Cryptography
Unit
Hardware RNG
Exponentiation Unit
AHB Slave/
South AHB 133.32 MHz x 32 bits
APB
Master
Bridge
USB-Host
Controller V. 2.0 Expansion Bus
High-Speed is not
Supported
8/16/32 bit + Parity
North AHB 133.32 MHz x 32 bits
North AHB
Arbiter
AHB/AHB
Queue
Manager Bridge
bv
South AHB
Arbiter
PCI Controller
Intel XScale
Controller
32 bit at 33/66 MHz
Master on North AHB
Bus Arbiters
AHB Slave / APB Master
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
DDRI Memory
Controller Unit
32 Bit
with no ECC
®
Processor
32-Kbyte I-Cache
32-Kbyte D-Cache
2-Kbyte Mini D-Cache
Max speed = 533 MHz
Developer's Manual
B5024 -002
47