Udc Data Register 4 - Intel IXP45X Developer's Manual

Register Name:
0 x C800B200
Hex Offset Address:
Register
Universal Serial Bus Device Endpoint 3 Data Register
Description:
Access: Write
31
Bits
31:8
7:0
8.5.34

UDC Data Register 4

Endpoint 4 is a double-buffered, isochronous OUT endpoint that is 256 bytes deep. The
UDC generates an interrupt when the EOP is received.
Because it is double-buffered, up to two packets of data may be ready. The data can be
removed from the UDC via a direct read from the Intel XScale processor. If one packet
is being removed and the packet behind it has already been received, the UDC issues a
NAK to the host the next time it sends an OUT packet to Endpoint 4.
This NAK condition remains in place until a full packet space is available in the UDC at
Endpoint 4.
Register Name:
0 x C800B400
Hex Offset Address:
Register
Universal Serial Bus Device Endpoint 4 Data Register
Description:
Access: Read
31
Bits
31:8
7:0
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
344
® ®
Intel IXP45X and Intel
16 15
(Reserved)
X
Resets (Above)
Register
Name
Reserved for future use.
DATA Top of endpoint data currently being loaded.
(Reserved)
X
Resets (Above)
Register
Name
Reserved for future use.
DATA Top of endpoint data currently being read.
IXP46X Product Line of Network Processors—USB 1.1 Device
UDDR3
0x00000000
Reset Hex Value:
Bits
UDDR3
Description
UDDR4
0x00000000
Reset Hex Value:
Bits
UDDR4
Description
Controller
8 7
(8-Bit Data)
0 0 0 0 0 0 0
(UDDR4)
8 7
(8-Bit Data)
0 0 0 0 0 0 0
August 2006
Order Number: 306262-004US
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0
0
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