Previous Master And Slave; Miscellaneous - Intel IXP45X Developer's Manual

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• Event type 39: PMU registers ESR0, ESR1 programmed to 0x27272727
PCEC [0-7] contains the core memory bus read latency (from Intel XScale
processor to DDR request to valid data back for each of the eight outstanding read
requests possible from the Intel XScale processor to memory).
• Event type 40: PMU register ESR0 programmed to 0x00002828
PEC0 (AHB North) and PEC1 (AHB South) contains the AHB bus Read latency (from
request to valid data back for each of the AHB bus ports).
Note: The MCU is PMU event 3 on AHB North and event 5 on AHB South.
16.3.4.4 Events
When not halted, a counter will count the cycles an event is "TRUE." The event
descriptions are listed above. To alleviate the wiring of redundant events into a very
large event mux, not all events are connected to every counter. Instead, the allocation
of events is intended to be a compromise between flexibility and simplicity. The basic
philosophy is that you should be able to measure all attributes about a given device, all
of the same attributes about a number of devices, or a subset of the two. An attempt is
made to maximize the flexibility but any conceivable combination of performance
metrics may not fit into 8 counter's worth of information or the chosen eight may not
be all accessible at the same time. To acquire any given group of metrics, it may be
necessary to repeat two passes of the same operations. There are some natural
inaccuracies that will result as a consequence of multiple passes unless extreme care is
taken to make the two passes identical.
16.4

Previous Master and Slave

The PMU provides a register that indicates the last masters and the slave they accessed
on both the North and South AHB busses. The master value stored is determined from
the HMASTER signal, which is simply the grants to the master devices. Whenever this
signal changes and there is a bus transaction the register bits will update. The slave
value stored is determined from the HSELx signal. Whenever the slave selected
changes and there is a bus transaction these register bits will update.
The PMSR will also lock the current master/slave in the case of an AHB error signal.
There are three reasons for an AHB error signal, an unsupported bus operation to a
slave, an uncorrectable error by a slave, and an out-of-range address. In the first two
cases, the HSEL field will contain the device which was being addressed, and in the
third case the HSEL field will contain 0xF. The first occurrence of an error signal on a
bus will cause the master and slave fields to be updated to the current value, the
"stuck" bit appropriate for the north and south fields will be set, and further updates
blocked until the "stuck" bit has been reset (by writing a '1' to the bit position). Multiple
error conditions are not supported, and any subsequent errors after the first are
ignored.
16.5

Miscellaneous

16.5.1 Interrupts
Each of the counters has an associated overflow flag. These flags are readable from the
PMU Status Register (PSR). The pmu_overflow_int interrupt is the logic OR of all the
overflow flags. The flags and interrupt are cleared when the register is written with
ones in the overflow positions. Setting an overflow condition from the counter takes
precedence over resetting the interrupt. If the counter overflows on the exact same
cycle the status is being reset, the overflow will be set.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
792
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—Performance Monitoring
Unit (PMU)
August 2006
Order Number: 306262-004US