Pci Controller South Ahb Transactions; Pci Controller Functioning As Bus Initiator; Command Type For Pci Controller Configuration And Status Register Accesses - Intel IXP45X Developer's Manual

Table 194.

Command Type for PCI Controller Configuration and Status Register Accesses

Command Value
pci_crp_ad_cbe[19:16
0x2 – 0xF
10.2.6

PCI Controller South AHB Transactions

The PCI Controller provides access to internal functionality within the IXP45X/IXP46X
network processors. The PCI Controller provides access to the South AHB through the
AHB Target Interface and the AHB Master Interface. The AHB Target Interface is used
to accept transaction request from other AHB Masters. The AHB Master Interface is
used to initiate transaction requests to other AHB Targets. The two DMA channels as
well as the PCI Target Interface use the AHB Master Interface.
The AHB Target Interface can accept 8-bit (1 Byte) transactions, 16-bit transactions,
and 32-bit transactions. Due to the South AHB not using byte enables, all 16-bit
transactions to the PCI Controller AHB Target Interface must be implemented as
consecutive-byte addresses. AHB protocol requires that 16-bit accesses be half-word
address aligned, address bit 0 must be 0. Inability to do this will result in multiple byte
wide transactions.
The AHB Master interface will initiate 8-bit (1 Byte) transactions and 32-bit (word)
transactions only. The DMA engines will initiate only 32-bit transactions. PCI Target
Interface initiated transactions will be 32-bit transactions. Sub 32-bit transactions —
initiated by the PCI Target Interface — will be implemented as multiple 8-bit
transactions initiated by the PCI Controller AHB Master on the AHB. For information on
prioritization of the three functional blocks that use the PCI Controller AHB Master
Interface, see next section that describes
on page
10.2.7

PCI Controller Functioning as Bus Initiator

The IXP45X/IXP46X network processors can be used to initiate PCI transactions in one
of three ways:
• Using the Non-Pre-fetch Registers — described in
Host" on page 501
The Non-Pre-fetch Registers allow various single 32-bit word PCI Cycles to be
produced as well as 8 and 16 bit transfers. The Non-Pre-fetch Registers can be
used to initiate Type 0 Configuration Cycles, Type 1 Configuration Cycles, Memory
Cycles, I/O Cycles, and Special Cycles.
• Writing to the PCI Memory Cycle Address Space located between AHB address
0x48000000 and 0x4BFFFFFF as described in
Configuration and Status Registers for Data Transactions" on page 505
• Using the PCI Controller DMA channels — described in
page 536
The remainder of the section shows example of each cycle type that may be initiated.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Develepor's Manual
512
®
Intel IXP45X and Intel
Command
Type
]
0x0 Read
0x1 Write
(Reserved)
512.
®
IXP46X Product Line of Network Processors—PCI Controller
Initiates a read of the PCI Controller Configuration and Status
Register Accesses
Initiates a write to the PCI Controller Configuration and Status
Register Accesses
Reserved for future use. Use of these values produce
unpredictable results.
"PCI Controller Functioning as Bus Initiator"
"PCI Controller Configured as
"Initializing PCI Controller
Description
"PCI Controller DMA" on
August 2006
Order Number: 306262-004US