Hss Registers And Clock Configuration; Hss Clock And Jitter - Intel IXP45X Developer's Manual

It can help isolate a problem by eliminating the HSS coprocessor and all blocks further
up the line as a source of a problem, if the system works correctly in loopback mode
this indicates that a problem (if one exists) is within blocks further down the system.
All TX and RX FIFOs should be empty before loopback is attempted. The HSS must
synchronize to the frame pulse before any operations commence. The user is free to
select either an internal or external frame pulse and clock.
When using the internal frame pulse/clock, the TX frame pulse/clock is internally
looped over to the RX side. If using the external frame pulse/clock, the clock/frame
pulse must be supplied on the TX frame pulse/clock pins, this is then automatically sent
to the RX logic also, there is no need to supply any signals on the rx pins.
No data is sent or received to/from the outside world while in loopback mode. This
mode can only be directly activated by the NPE Core.
13.4

HSS Registers and Clock Configuration

There are numerous Control and Status Registers (CSRs) contained within the NPE/HSS
interface of the IXP45X/IXP46X network processors that are used to configure the
many unique HSS settings discussed in this manual. The functional details of these
registers are not exposed within any documentation for the IXP45X/IXP46X network
processors and are reserved for use by NPE firmware only. The IxHssAcc API, however,
provides indirect access to the these registers to allow the complete control and
configuration of all HSS features enabled by a particular IXP400 software. The Intel
IXP400 Software Programmer's Guide should be referenced for specific information
regarding use of the IxHssAcc API.
There is one register titled the HSS Clock Divider Register that provides a means to
generate a unique data clock for each of the two HSS interfaces for the IXP45X/IXP46X
network processors. The IxHssAcc API will configure the HSS clock divider register with
the appropriate values depending on which clock frequencies is selected, being
512 KHz, 1.536 MHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, and 8.192 MHz. This is
discussed further in the next section:
13.4.1

HSS Clock and Jitter

Each of the two High-Speed Serial (HSS) interfaces on the IXP45X/IXP46X network
processors can be configured to generate an output clock on the HSS_TXCLK and
HSS_RXCLK pins. This output clock, however, is not as accurate and stable as using an
external oscillator. That is because the HSS clock is based on the internal, 133.32-MHz
AHB bus. This frequency does not divide down easily. Subsequently, jitter and error are
introduced into the resultant HSS output clock.
If developers are clocking a framer, DAA, or other device with a sensitive input PLL,
they should use an external clock.
To provide developers with additional data, this chapter contains five tables:
• Table 238, "HSS Tx/Rx Clock Output" on page 735
• Table 239, "HSS Tx/Rx Clock Output Frequencies and PPM Error" on page 735
• .................Table 240, "HSS Tx/Rx Clock Output Frequencies and Associated Jitter
Characterization" on page 735
• Table 241, "HSS Frame Output Characterization" on page 736
• Table 242, "Jitter Definitions" on page 736
The jitter and error calculations, in the following tables, are valid only for IXP400
software Release 1.4 and later.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
734
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors—HSS Coprocessor
®
August 2006
Reference Number: 004US