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3.6.9
Transmit Register
The TX register is the debug handler transmit buffer. The debug handler sends data to
the debugger through this register.
Table 45.
TX Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: unpredictable
Bits
31:0
Since the TX register is accessed by the debug handler (using MCR/MRC) and the
debugger (through JTAG), handshaking is required to prevent the debug handler from
writing new data before the debugger reads the previous data.
The TX register handshaking is described in
3.6.10
Receive Register
The RX register is the receive buffer used by the debug handler to get data sent by the
debugger through the JTAG interface.
Table 46.
RX Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: unpredictable
Bits
31:0
Since the RX register is accessed by the debug handler (using MRC) and the debugger
(through JTAG), handshaking is required to prevent the debugger from writing new
data to the register before the debug handler reads the previous data out. The
handshaking is described in
3.6.11
Debug JTAG Access
There are four JTAG instructions used by the debugger during software debug: LDIC,
SELDCSR, DBGTX and DBGRX. LDIC is described in
page
139. The other three JTAG instructions are described in this section.
SELDCSR, DBGTX and DBGRX use a common 36-bit shift register (DBG_SR). New data
is shifted in and captured data out through the DBG_SR. In the UPDATE_DR state, the
new data shifted into the appropriate data register.
®
®
Intel
IXP45X and Intel
IXP46X Product Line of Network Processors
Developer's Manual
124
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors—Intel XScale
Access
SW Read / Write
JTAG Read-only
Access
SW Read-only
JTAG Write-only
"RX Register Ready Bit (RR)" on page
8
TX
Description
Debug handler writes data to send to debugger
Table 43, "TX Handshaking" on page
8
RX
Description
Software reads to receives data/commands from
debugger
"Downloading Code in ICache" on
Order Number: 306262-004US
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Processor
7
6
5
4
3
2
1
0
123.
7
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5
4
3
2
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121.
August 2006
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