Master Transactions; I 2 C Bus Operation - Intel IXP45X Developer's Manual

I2C Bus Interface Unit—Intel
Table 279. Master Transactions (Sheet 1 of 2)
2
I C Master
Action
Generate clock
output
Write target
slave address to
IDBR
Write R/W# Bit
to IDBR
Signal START
Condition
Initiate first
data byte
transfer
Arbitrate for I
Bus
Write one data
byte to the
IDBR
Wait for
Acknowledge
from slave-
receiver
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
Mode of
Operation
• The master always drives the SCL line.
Master-transmit • The ICCR register is written.
Master-receive • The SCL Enable bit must be set.
• The Unit Enable bit must be set.
• The CPU writes to IDBR bits 7-1 before a START condition is
Master-transmit
• First 7 bits sent on bus after START.
Master-receive
• See
• The CPU writes to the least significant IDBR bit with the target slave
Master-transmit
• If low, the master remains a master-transmitter. If high, the master
Master-receive
• See
• See "Generate clock output" above.
• Performed after the target slave address and the R/W# bit are in the
Master-transmit
• CPU sets the START bit.
Master-receive
• CPU sets the Transfer Byte bit which initiates the start condition.
• See
• CPU writes byte to IDBR
• I
Master-transmit
Master-receive
• I
• If two or more masters signal a start within the same clock period,
• The I
2 Master-transmit
C • If the I
Master-receive
• If I
• The system designer must ensure the boundary conditions described
• Data transmit mode of I
• Occurs when the IDBR Transmit Empty ISR bit is set and the
Master-transmit
only
•
• As a master-transmitter, the I
Master-transmit
only
• See
Definition
enabled.
"Start and Stop Bus States" on page
address.
transitions to a master-receiver.
"Data and Addressing Management" on page
IDBR.
"Start and Stop Bus States" on page
2
C Bus Interface Unit transmits the byte when the Transfer Byte bit
is set.
2
C Bus Interface Unit clears the Transfer Byte bit and sets the IDBR
Transmit Empty bit when the transfer is complete.
arbitration must occur.
2
C Bus Interface Unit will arbitrate for as long as necessary.
Arbitration takes place during slave address, R/W# bit, and data
transmission and continues until all but one master loses the bus.
No data is lost during arbitration.
2
C Bus Interface Unit loses arbitration, it will set the
Arbitration Loss Detect ISR bit after byte transfer is complete and
transition to slave-receive (default) mode.
2
C Bus Interface Unit loses arbitration while attempting to send
the target address byte, the I
resend it when the bus becomes free.
in "I2C Bus Operation" on page 881
2
C master operation.
Transfer Byte bit is clear. If enabled, the IDBR Transmit Empty
Interrupt is signalled to the IXP45X/IXP46X network processors.
will write 1 data byte to the IDBR, set the appropriate START/
CPU
STOP bit combination, and then set the Transfer Byte bit to send the
data. Eight bits are written on the serial bus followed by a STOP if
requested.
clock for the acknowledge pulse. The I
responsible for releasing the SDA line to allow slave-receiver Ack
transmission.
"I2C Acknowledge" on page
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
879.
882.
879.
2
C Bus Interface Unit will attempt to
do not occur.
2
C Bus Interface Unit will generate the
2
C Bus Interface Unit is
883.
Developer's Manual
887