Asynchronous Schedule Traversal: Start Event; Reclamation Status Bit (Usbsts Register) - Intel IXP45X Developer's Manual

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Table 174. Typical Low- /Full-Speed Transaction Times (Sheet 2 of 2)
Transaction Attributes
Speed
Size
Type
An AsyncSchedSleepTime value of 10 μs provides a reasonable relaxation of the system
memory load and still provides a good level of service for the various transfer types and
payload sizes. For example, say we detect an empty list after issuing a start-split for a
64-byte full-speed bulk request. Assuming this is the only thing in the list, the host
controller will get the results of the full-speed transaction from the hub during the fifth
complete-split request. If the full-speed transaction was an IN and it nak'd, the 10μs
sleep period would allow the host controller to get the NAK results on the first
complete-split.
9.14.8.5

Asynchronous Schedule Traversal: Start Event

Once the HC has idled itself via the empty schedule detection
"Empty Asynchronous Schedule Detection" on page
begin processing from the Periodic Schedule at the beginning of each micro-frame. In
addition, it may have idled itself early in a micro-frame. When this occurs (idles early in
the micro-frame) the HC must occasionally re-activate during the micro-frame and
traverse the asynchronous schedule to determine whether any progress can be made.
The requirements and method for this restart are described in
"Restarting Asynchronous Schedule Before EOF" on page
Start Events are defined to be:
• Whenever the host controller transitions from the periodic schedule to the
asynchronous schedule. If the periodic schedule is disabled and the asynchronous
schedule is enabled, then the beginning of the micro-frame is equivalent to the
transition from the periodic schedule, or
• The asynchronous schedule traversal restarts from a sleeping state (see
9.14.8.4, "Restarting Asynchronous Schedule Before EOF" on page
9.14.8.6

Reclamation Status Bit (USBSTS Register)

The operation of the empty asynchronous schedule detection feature
"Empty Asynchronous Schedule Detection" on page
management of the Reclamation bit in the USBSTS register. The host controller tests
for an empty schedule just after it fetches a new queue head while traversing the
asynchronous schedule (See
It is required that the host controller sets the Reclamation bit to a one whenever an
asynchronous schedule traversal Start Event, as documented in
Schedule Traversal: Start Event" on page
to a one whenever the host controller executes a transaction while traversing the
asynchronous schedule (see
The host controller sets the Reclamation bit to a zero whenever it finds a queue head
with its H-bit set to a one. Software should only set a queue head's H-bit if the queue
head is in the asynchronous schedule. If software sets the H-bit in an interrupt queue
head to a one, the resulting behavior is undefined. The host controller may set the
Reclamation bit to a zero when executing from the periodic schedule.
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
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IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller
Footprint
(Time)
FS
~12 µs
8
Cntrl
Section 9.14.10.1, "Fetch Queue Head" on page
Section 9.14.10.3, "Execute Transaction" on page
Description
Approximate typical for 8-byte bulk/control (i.e. setup)
435), it will naturally activate and
435) depends on the proper
438, occurs. The Reclamation bit is also set
(Section 9.14.8.3,
Section 9.14.8.4,
435. Asynchronous schedule
Section
435).
(Section 9.14.8.3,
443).
"Asynchronous
444).
August 2006
Order Number: 306262-004US