Cp 14 Trace Buffer Register Summary; Checkpoint Register (Chkptx) - Intel IXP45X Developer's Manual

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Intel XScale Processor—Intel
Table 48.

CP 14 Trace Buffer Register Summary

CP14 Register Number
Any access to the trace buffer registers in User mode will cause an undefined
instruction exception. Specifying registers which do not exist has unpredictable results.
3.6.12.1.1 Checkpoint Registers
When the debugger reconstructs a trace history, it is required to start at the oldest
trace buffer entry and construct a trace going forward. In fill-once mode and wrap-
around mode when the buffer does not wrap around, the trace can be reconstructed by
starting from the point in the code where the trace buffer was first enabled.
The difficulty occurs in wrap-around mode when the trace buffer wraps around at least
once. In this case the debugger gets a snapshot of the last N control flow changes in
the program, where N <= size of buffer. The debugger does not know the starting
address of the oldest entry read from the trace buffer. The checkpoint registers provide
reference addresses to help reduce this problem.
Table 49.

Checkpoint Register (CHKPTx)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: Unpredictable
Bits
31:0
The two checkpoint registers (CHKPT0, CHKPT1) on the IXP45X/IXP46X network
processors provide the debugger with two reference addresses to use for re-
constructing the trace history.
When the trace buffer is enabled, reading and writing to either checkpoint register has
unpredictable results. When the trace buffer is disabled, writing to a checkpoint register
sets the register to the value written. Reading the checkpoint registers returns the
value of the register.
In normal usage, the checkpoint registers are used to hold target addresses of specific
entries in the trace buffer. Only direct and indirect entries get check-pointed. Exception
and roll-over messages are never check-pointed. When an entry is check-pointed, the
processor sets bit 6 of the message byte to indicate this (refer to
Byte Formats)
When the trace buffer contains only one check-pointed entry, the corresponding
checkpoint register is CHKPT0. When the trace buffer wraps around, two entries will
typically be check-pointed, usually about half a buffers length apart. In this case, the
first (oldest) check-pointed entry read from the trace buffer corresponds to CHKPT1,
the second check-pointed entry corresponds to CHKPT0.
Although the checkpoint registers are provided for wrap-around mode, they are still
valid in fill-once mode.
August 2006
Order Number: 306262-004US
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IXP45X and Intel IXP46X Product Line of Network Processors
Register Name
11 Trace Buffer Register (TBREG)
12 Checkpoint 0 Register (CHKPT0)
13 Checkpoint 1 Register (CHKPT1)
Access
Read/Write
CHKPTx
CHKPTx:
target address for corresponding entry in trace buffer
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
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Description
Table 51., Message
Developer's Manual
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