Eight-Word Inbound Read With Master Wait States - Intel IXP45X Developer's Manual

Expansion Bus Controller—Intel
Processors
12.4.5.10

Eight-Word Inbound Read with Master Wait States

Figure 159. Eight-Word Inbound Read with Master Wait States
- 0 - - 1 -
EX_CLK
EX_ IXPCS_N
EX_ ADDR
ADDR0
EX_RD_N
EX_WR_N
EX_BE_N
EX_ BURST
EX_ WAIT_N
EX_ DATA
EX_ PARITY
STATE
IDLE NOP
The above timing diagram shows a 8-word read with master introduced wait states.
The Expansion bus controller uses EX_ADDR[4:2] to determine which word is read from
its data fifo. The master can also stop the data burst in any cycle after EX_WAIT_N is
deasserted. In the above timing diagram, the external master drives EX_ADDR to X on
cycles 5,7,9, and 10; the master is allowed to drive EX_ADDR to X since EX_WAIT_N
was deasserted and because there was not a NOP in the previous cycle. If the external
master chose to insert a NOP cycle, it cannot drive EX_ADDR to X on the cycle following
the NOP cycle.
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network
- 3 - - 4 - - 5 -
- 2 -
DATA0
PAR0
WAIT DATA0
- 6 - - 7 - - 8 - - 9 -
ADDR1 ADDR2
DATA1
PAR1
DATA1 DATA1 DATA2
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
- 10 - - 11 - - 12 -
ADDR7
DATA2 DATA7
PAR2 PAR7
DATA2 DATA7 DATA7
Developer's Manual
- 13 -
IDLE
B4457-01
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