Intel
Figure 187. Operating System Timer Block Diagram
sel
pclk
sc_en
'1'
prescale
sel
pclk
sc_en
'1'
sel
pclk
sc_en
'1'
prescale
18.4
Theory of Operation
The OST supports four timers, the first is a watchdog timer, the second a free-running
timestamp timer and the last two are general-purpose timers capable of generating
interrupts at predetermined intervals.
All of the registers/counters operate on the APB bus clock by default. By writing a value
into separate configuration and prescale registers, a prescaled enable can be used for
each timer. Each timer, except for watchdog timer, can also enable a 3/4 scale function
to emulate a 20-ns clock from a 66.667-MHz input clock. The 3/4 scaler can also be
used in combination with the prescaler.
18.4.1
Watchdog Timer Operation
The watchdog timer is used by the software to monitor inactivity. The watchdog timer is
composed of four components:
• A 32-bit writable down counter — (
• A 3-bit enable register — (
• A 16-bit key register — (
• A 5-bit status register — (
The ost_wdog_key register can be written at any time over the APB bus. However, all
the watch-dog registers can only be written to when the ost_wdog_key register
contains the value 0x482E (this value referred to from here on as "key-value"). A write
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Intel
IXP45X and Intel
IXP46X Product Line of Network Processors
Developer's Manual
818
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IXP45X and Intel
IXP46X Product Line of Network Processors—Operating System Timer
pclk
Timestamp Timer
en
ts_
Compare register
sel
pclk
General Purpose
en
tim0_
Reload Register 0
prescale
sel
pclk
General Purpose
en
Reload Register 1
tim1_
sel
pclk
Watchdog Timer
WD Enable Register
WD Key Register
ost_wdog_key
ost_sts)
Timestamp *
Timestamp config *
Timer 0
OST_config0 *
Timer 1
Outputs
OST_config1 *
ost_wdog
)
ost_wdog_enab
)
)
Ost Status
Register
APB Interface
ost_ts_int
ost_time0_int
Timer
ost_time1_int
ost_wdog_int
ost_wdog_reset
Order Number: 306262-004US
B4318-01
August 2006
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