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PCI Controller—Intel
IXP45X and Intel
10.2.5
Initializing the PCI Controller Configuration Registers
The PCI Base Address Registers along with any other pertinent PCI Configuration
Registers, located in the PCI Controller PCI Configuration Register space, must be
initialized by the Intel XScale processor when the IXP45X/IXP46X network processors
are configured as the PCI host. The PCI Base Address Registers must be initialized by
an external PCI device when the IXP45X/IXP46X network processors are configured as
a PCI option.
The PCI Base Address Registers — along with any other registers in the PCI
Configuration Space — will be accessed by the Intel XScale processor using three
Configuration and Status Registers:
• PCI Configuration Port Address/Command/Byte Enables (PCI_CRP_AD_CBE)
Register
• PCI Configuration Port Write Data (PCI_CRP_WDATA) Register
• PCI Configuration Port Read Data (PCI_CRP_RDATA) Register.
The IXP45X/IXP46X network processors are a single-function, Type 0 Configuration
space when functioning as a PCI option. For detailed information on the values to
program the PCI Controller Configuration and Status Registers, see the PCI Local Bus
Specification, Rev. 2.2.
The PCI Configuration Port Write Data (PCI_CRP_WDATA) Register is a 32-bit register
that is used to place the data that is to be written into the PCI Configuration Space.
The PCI Configuration Port Read Data (PCI_CRP_RDATA) Register is a 32-bit register
that is used to capture the data that is returned from the PCI Configuration Space. The
PCI Configuration Port Address/Command/Byte Enables (PCI_CRP_AD_CBE) Register
provides the address, byte enables, and control for the read and write access to the PCI
Configuration Space from the internal side of the IXP45X/IXP46X network processors.
• Bits 23:20 of the PCI Configuration Port Address/Command/Byte Enables
(PCI_CRP_AD_CBE) Register specify the byte enables for the access to the PCI
Configuration Space
These bits directly correspond to the four - byte field associated with the PCI
Configuration Port Write Data (PCI_CRP_WDATA) Register.
shows the mapping of the byte enables of the PCI Configuration Port Address/
Command/Byte Enables (PCI_CRP_AD_CBE) Register to the byte lane fields of the
PCI Configuration Port Write Data (PCI_CRP_WDATA) Register.
• Bits 7:2 of the PCI Configuration Port Address/Command/Byte Enables
(PCI_CRP_AD_CBE) Register specify the address for the register access within the
64 32-bit Word PCI Configuration Space.
The 64 32-bit Word PCI Configuration Space is shown in
• Bits 19:16 of the PCI Configuration Port Address/Command/Byte Enables
(PCI_CRP_AD_CBE) Register specify the command to execute on the PCI
Configuration Space. The only two commands currently defined are read and write.
Table 194 on page 512
Configuration Space. When a read command is written into the command field of
the PCI Configuration Port Address/Command/Byte Enables (PCI_CRP_AD_CBE)
Register along with the appropriate address of the PCI Configuration register to be
accessed, the data from the address requested will be returned to the PCI
Configuration Port Read Data (PCI_CRP_RDATA) Register.
A master on the AHB bus can then read the PCI Configuration Port Read Data
(PCI_CRP_RDATA) Register. For example:
1. PCI_CRP_AD_CBE is written with hexadecimal 0x00300004, which causes the
contents of the PCI Control Register/Status Register (PCI_SRCR) to be written into
the PCI_CRP_RDATA register.
August 2006
Order Number: 306262-004US
®
IXP46X Product Line of Network Processors
shows valid command codes for accessing the PCI
®
Intel
IXP45X and Intel
Table 192 on page 511
Table 193 on page
®
IXP46X Product Line of Network Processors
Develepor's Manual
511.
509
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