Data And Addressing Management; Addressing A Slave Device; I 2 C Acknowledge - Intel IXP45X Developer's Manual

Intel
The SCL transition period is the amount of time the clock spends in the high or low
state. When wait states are inserted or synchronization with another master is
necessary, the I
Note: The ICCR register is reserved on the IXP45X/IXP46X network processors. The I
master driver clock, SCL, has the option of running at 100-Kbps or 400-Kbps. This is
set in the I
ICR" on page
21.5.2

Data and Addressing Management

Data and slave addressing is managed via the I
2
I C Slave Address Register (ISAR). The IDBR (see
page 902) contains data or a slave address and R/W# bit. The ISAR contains the
processor's programmable slave address. Data coming into the I
the IDBR after a full byte is received and acknowledged. To transmit data, the CPU
writes to the IDBR, and the I
Byte bit in the ICR is set. See
When the I
1. Software writes data to the IDBR over the internal bus.
This initiates a master transaction or sends the next data byte after the ISR[IDBR
Transmit Empty] bit is set.
2. The I
3. When enabled, an IDBR Transmit Empty interrupt is signalled when a byte is
transferred on the I
4. When the I
IDBR and a STOP condition is not in place, the I
CPU writes a new value into the IDBR and sets the ICR[Transfer Byte] bit.
When the I
1. The processor reads IDBR data over the internal bus after the IDBR Receive Full
interrupt is signalled.
2. The I
completes.
3. The I
For acknowledge pulse information in receiver mode, see
page
4. After the CPU reads the IDBR, the I
the ICR[Transfer Byte] bit, allowing the next byte transfer to proceed.
21.5.2.1

Addressing a Slave Device

As a master device, the I
This byte consists of the slave address for the intended device and a R/W# bit for
transaction definition. The slave address and the R/W# bit are written to the IDBR (see
"I2C Data Buffer Register - IDBR" on page
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
882
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—I2C Bus Interface Unit
2
C unit performs the necessary clock synchronization.
2
C Control Register (IDBR) (see
897).
2
C unit passes this onto the serial bus when the Transfer
"I2C Control Register - ICR" on page
2
C unit is in master- or slave- transmit mode:
2
C unit transmits the data from the IDBR when the ICR[Transfer Byte] is set.
2
C bus and the acknowledge cycle is complete.
2
C bus is ready to transfer the next byte before the CPU has written the
2
C unit is in master- or slave-receive mode:
2
C unit transfers data from the shift register to the IDBR after the Ack cycle
2
C unit inserts wait states until the IDBR is read.
883.
2
C unit must compose and send the first byte of a transaction.
Section 21.10.1, "I2C Control Register -
2
C Data Buffer Register (IDBR) and the
"I2C Data Buffer Register - IDBR" on
2
C unit inserts wait states until the
"I2C Acknowledge" on
2
C unit writes the ICR[AckNak] Control bit and
902).
2
C unit's
2
C unit is received into
897.
August 2006
Order Number: 306262-004US