Table of Contents
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Contents-Intel
IXP45X and Intel
Contents
1.0
Introduction............................................................................................................. 38
1.1
About This Document......................................................................................... 38
1.2
Intended Audience ............................................................................................ 38
1.3
How to Read This Document ............................................................................... 38
1.4
Other Relevant Documents ................................................................................. 38
1.5
Terminology and Conventions ............................................................................. 39
1.5.1
Number Representation........................................................................... 42
1.5.2
Signal-Naming Convention ...................................................................... 42
1.5.3
Register Legend ..................................................................................... 43
2.0
Functional Overview ................................................................................................ 44
2.1
Key Functional Units .......................................................................................... 48
2.1.1
Network Processor Engines (NPEs)............................................................ 48
2.1.2
Internal Bus .......................................................................................... 49
2.1.2.1
2.1.2.2
2.1.2.3
2.1.2.4
2.1.3
MII/SMII Interfaces ................................................................................ 51
2.1.4
UTOPIA Level 2 ...................................................................................... 51
2.1.5
Universal Serial Bus (USB) Interfaces........................................................ 52
2.1.5.1
2.1.5.2
2.1.6
PCI Controller ........................................................................................ 52
2.1.7
DDRI SDRAM Controller .......................................................................... 53
2.1.8
Expansion Interface ................................................................................ 54
2.1.9
High-Speed, Serial Interfaces................................................................... 56
2.1.10 UARTs .................................................................................................. 56
2.1.11 GPIO .................................................................................................... 56
2.1.12 Internal Bus Performance Monitoring Unit (IBPMU) ..................................... 57
2.1.13 Interrupt Controller ................................................................................ 57
2.1.14 Timers .................................................................................................. 58
2.1.15 IEEE-1588 Hardware Assist ..................................................................... 58
2.1.16 Synchronous Serial Protocol Interface ....................................................... 58
2.1.17 I2C Interface ......................................................................................... 59
2.1.18 AES/DES/SHA/MD-5 ............................................................................... 59
2.1.19 Cryptography Unit .................................................................................. 59
2.1.20 Queue Manager...................................................................................... 60
2.2
2.2.1
Super Pipeline........................................................................................ 62
2.2.2
Branch Target Buffer .............................................................................. 63
2.2.3
Instruction Memory Management Unit ....................................................... 63
2.2.4
Data Memory Management Unit ............................................................... 64
2.2.5
Instruction Cache ................................................................................... 64
2.2.6
Data Cache ........................................................................................... 65
2.2.7
Mini-Data Cache..................................................................................... 65
2.2.8
Fill Buffer and Pend Buffer ....................................................................... 65
2.2.9
Write Buffer........................................................................................... 66
2.2.10 Multiply-Accumulate Coprocessor ............................................................. 66
2.2.11 Performance Monitoring Unit .................................................................... 66
2.2.12 Debug Unit ............................................................................................ 67
®
3.0
Processor ........................................................................................... 69
August 2006
Order Number: 306262-004US
®
IXP46X Product Line of Network Processors
North AHB ............................................................................... 49
South AHB ............................................................................... 50
Memory Port Interface............................................................... 50
APB Bus .................................................................................. 51
USB 1.1 Device Interface ........................................................... 52
USB 2.0 Host Interface .............................................................. 52
®
Processor ..................................................................................... 60
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®
Intel
IXP45X and Intel
IXP46X Product Line of Network Processors
Developer's Manual
3
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