Intel IXP45X Developer's Manual page 752

Intel
Figure 184. UART Block Diagram
To
®
Intel IXP46X
Interrupt
Network
Processor
Interrupt
Controller
To
®
Intel XScale
Processor
clk_uart
14.4 Theory of Operation
The following sections provide a detailed description of configuring the UART interfaces
for operation.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
752
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—Universal Asynchronous
Control and
Status
Registers
APB
Interface
Baud Rate
Generator
Receiver-Transmitter (UART)
txd
Transmit Shift Reg
Transmit Hold
Register
Transmit FIFO
(64 Bytes)
Receive Shift
Register
Receive Buffer
Register
Receive FIFO
(64 Bytes)
Modem Control
Signals
Order Number: 306262-004US
rxd
rts_n
cts_n
B4322-03
August 2006