Ethernet Coprocessor Mdio Interface - Intel IXP45X Developer's Manual

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Ethernet MACs—Intel IXP45X and Intel
6.1.3

Ethernet Coprocessor MDIO Interface

The Management Data Interface is a two-wire interface that supports configuration of
an xMII Interface on the IXP45X/IXP46X network processors. The Management Data
Interface consists of the Management Data Input/Output (MDIO) signal and the
Management Data Clock (MDC). The Management Data Input/Output signal is a
bidirectional signal that is used to transfer control, configuration, and status
information between the IXP45X/IXP46X network processors and any peripheral
devices connected to the xMII interfaces.
The Ethernet Coprocessor is initiated three times to support three Ethernet PHYs
outside the device. However, only the MDC and MDIO pins of one of the coprocessors
(Ethernet B) were brought out and they are used to program both Ethernet PHYs.
The Management Data Clock can be configured as an input or an output, enabling the
IXP45X/IXP46X network processors to source the Management Data Clock or enable an
external device to source the clock. The Management Date Clock is used to clock the
data sent on the Management Data Input/Output Signal.
Data transfers will be initiated over the MDIO using the MDIO Command Register
(MDIOCMD). The MDIO Command Register is broken into four 8-bit registers that make
up a full 32-bit command word.
If data is to be sent to the PHY over the MDIO interface, the Intel XScale processor will
write a value to each of the four command words in sequential order:
• MDIO Command 1 (MDIOCMD1) Register and MDIO Command 2 (MDIOCMD2)
Register will contain the 16 bits of data that the destination PHY will receive.
• MDIO Command 3 (MDIOCMD3) Register and MDIO Command 4 (MDIOCMD4)
Register will determine which PHY number is to be addressed, the internal register
of the addressed PHY, the direction of the access (read/write), and when to begin
the access.
There can be a limit of 32 physical ports with a limit of 32 registers per physical port
that may be addressed.
MDIOCMD3 makes up bits (23:16) of MDIOCMD and MDIOCMD4 make up bits (31:24):
• Bits (25:21) of MDIOCMD are used to select the physical interface that is to accept
the transmitted data or return the requested data.
• Bits (20:16) of MDIOCMD are used to select the register within the physical
interface that is to accept the transmitted data or return the requested data.
• Bit 26 of MDIOCMD is used to determine if the requested command is a read or a
write:
— Writing logic 1 to this bit will cause the transaction to be a write.
— Writing logic 0 to this bit will cause the transaction to be a read.
Setting Bit 31 of the MDIO Command (MDIOCMD) Register to logic 1 will initiate the
transfer. Bit 31 of MDIOCMD will remain at logic 1 until the transaction is complete.
Figure 30
Master (IXP45X/IXP46X network processors) to a physical interface (PHY) using the
MDIO interface.
As stated previously, when bit 26 of the MDIO Command (MDIOCMD) Register is set to
logic 0 the Intel XScale processor is requesting a read from a physical interface device
using the MDIO interface. The data that the physical interface returns from the MDIO
signal will be captured in the MDIO STATUS (MDIOSTS) Register.
August 2006
Order Number: 306262-004US
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IXP46X Product Line of Network Processors
shows an example of the data being written from the xMII Management
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
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