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Functional Overview—Intel
2
2.1.17
I
C Interface
2
The I
C Bus Interface Unit allows the IXP45X/IXP46X network processors to serve as a
master and slave device residing on the I
of a two-pin interface. SDA is the data pin for input and output functions and SCL is the
clock pin for reference and control of the I
2
The I
C bus allows the IXP45X/IXP46X network processors to interface to other I
peripherals and microcontrollers for system management functions. The serial bus
requires a minimum of hardware for an economical system to relay status and
reliability information on the IXP45X/IXP46X network processors subsystem to an
external device.
2
The I
C Bus Interface Unit is a peripheral device that resides on the IXP45X/IXP46X
network processors' APB. Data is transmitted to and received from the I
buffered interface. Control and status information is relayed through a set of memory-
mapped registers. Refer to the I
operation.
2
The I
C supports:
• Multi-master capabilities
• Slave capabilities
2
The I
C unit supports both fast-mode operation — at 400 Kbps — and standard mode
— at 100 Kbps. Fast mode logic levels, formats, capacitive loading and protocols
function the same in both modes. The I
or CBUS.
2.1.18
AES/DES/SHA/MD-5
The IXP45X/IXP46X network processors implement on chip hardware acceleration for
underlying security and authentication algorithms.
The encryption/decryption algorithms supported are AES, single pass AES-CCM, triple
DES. These algorithms are commonly found when implementing IPSec, VPN, WEP,
WEP2, WPA, and WPA2.
The authentication algorithms supported are MD-5, SHA-1, SHA-256, SHA-384, and
SHA-512. Inclusion of SHA-384 and SHA-512 allows 256-bit key authentication to pair
up with 256-bit AES support.
Note:
All the described NPE functions require Intel-supplied software executing on the NPEs.
For further information, see the Intel
information on the availability of the NPE software and its enabling functions, contact
your local sales representative.
2.1.19
Cryptography Unit
The Cryptography Unit consists of three major functions:
• Exponentiation Unit (EAU)
• Random Number Generator (RNG)
• Secure Hash Algorithm Unit (SHA)
The EAU supports various large number arithmetic operations. These operations include
modular exponentiation, modular reduction, multiply, add and subtract. These
operations are controlled through a set of memory mapped registers. Parameters for
and results of the operations are written in little-endian ordering into a RAM (contained
August 2006
Reference Number: 306262-004US
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors
2
C bus. The I
2
C bus.
2
C Bus Specification for complete details on I
2
C unit does not support I
®
IXP400 Software Programmer's Guide. For
®
®
Intel
IXP45X and Intel
IXP46X Product Line of Network Processors
2
C bus is a serial bus consisting
2
C bus via a
2
C 10-bit addressing
Developer's Manual
2
C
2
C bus
59
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