Ssp Control Register 1 (Sscr); Receive Fifo Interrupt Enable (Rie); Transmit Fifo Interrupt Enable (Tie); Loop Back Mode (Lbm) - Intel IXP45X Developer's Manual

Intel
Register
Bit Name
This field specifies the Data Size Selection.
0000 - Reserved, undefined operation
0001 - Reserved, undefined operation
0010 - Reserved, undefined operation
0011 - 4-bit data
0100 - 5-bit data
0101 - 6-bit data
0110 - 7-bit data
3:0 DSS 0111 - 8-bit data
1000 - 9-bit data
1001 - 10-bit data
1010 - 11-bit data
1011 - 12-bit data
1100 - 13-bit data
1101 - 14-bit data
1110 - 15-bit data
1111 - 16-bit data
20.5.2 SSP Control Register 1 (SSCR1)
The SSP Control Register 1 (SSCR1) contains nine bit fields that control various SSP
functions.
20.5.2.1

Receive FIFO Interrupt Enable (RIE)

The Receive FIFO Interrupt Enable (RIE) bit is used to mask or enable the Receive FIFO
service request interrupt. When RIE=0, the interrupt is masked, and the state of the
Receive FIFO Service Request (RFS) bit within the SSP Status Register is ignored by the
interrupt controller. When RIE=1, the interrupt is enabled, and whenever RFS is set to
one an interrupt request is made to the interrupt controller. Note that programming
RIE=0 does not affect the current state of RFS or the receive FIFO logic's ability to set
and clear RFS, it only blocks the generation of the interrupt request.
20.5.2.2

Transmit FIFO Interrupt Enable (TIE)

The Transmit FIFO Interrupt Enable (TIE) bit is used to mask or enable the transmit
FIFO service request interrupt. When TIE=0, the interrupt is masked and the state of
the Transmit FIFO Service Request (TFS) bit within the SSP Status Register is ignored
by the interrupt controller. When TIE=1, the interrupt is enabled, and whenever TFS is
set to one an interrupt request is made to the interrupt controller. Note that
programming TIE=0 does not affect the current state of TFS or the transmit FIFO
logic's ability to set and clear TFS, it only blocks the generation of the interrupt request.
20.5.2.3

Loop Back Mode (LBM)

The loop back mode (LBM) bit is used to enable and disable the ability of the SSP
transmit and receive logic to communicate. When LBM=0, the SSP operates normally.
The transmit and receive data paths are independent and communicate via their
respective pins. When LBM=1, the output of the transmit serial shifter is directly
connected to the input of the receive serial shifter internally.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
866
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—Synchronous Serial Port
Description
SSCR0 (Sheet 2 of 2)
Reset
Access
Value
0x0000 RW
August 2006
Order Number: 306262-004US