Internal Bus Arbiters; Priority Mechanism - Intel IXP45X Developer's Manual

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Internal Buses—Intel IXP45X and Intel
5.1

Internal Bus Arbiters

The IXP45X/IXP46X network processors contain two internal bus arbiters, one arbiter
for North AHB transactions and one arbiter for South AHB transactions. The arbiters are
used to ensure that at any particular time only one AHB master has access to a given
AHB. The arbiters perform this function by observing all of the AHB master requests to
the given AHB segment and deciding which AHB master will be the next owner of the
AHB.
The arbiters have a standard interface to all bus masters and split-capable slaves in the
system. Any AHB master can request an AHB at any cycle. The arbiters sample the AHB
requests. If the particular AHB master is requesting the AHB and is next in the round-
robin list, the arbiter will grant the master the AHB.
The arbiters also have the capability to handle split transfers. A split transfer is when:
• An AHB master request a read from a split capable AHB target
• The split-capable AHB target issues a split transfer indication to the arbiter
• The arbiter allows other transactions to take place on the AHB while the AHB
master that issued the request that resulted in the split transfer waits on the read
data to be returned from the split capable AHB target
• The split capable AHB target completes the read transaction and notifies the arbiter
• The arbiter will grant the AHB master that requested the split transfer the bus in
the normal round-robin progression
• The read data will be transferred from the split capable AHB target to the AHB
master that issued the request that resulted in the split transfer
All split capable AHB targets split a single AHB master read request at any given
instance. If the split capable AHB target receives another read request while servicing a
split transaction, the split capable AHB target will issue a retry. The only split capable
targets on the South AHB is the Expansion Bus. The only split capable target on the
North AHB is the AHB/AHB Bridge.
The arbiters send event information to the Performance Monitoring Unit (PMU) so that
the North AHB and South AHB performance can be observed. The events that may be
monitored are provided in the chapter "Performance Monitoring Unit," in the second
volume of this two-volume component specification.
The North AHB Arbiter is identical to the South AHB Arbiter in all respects except for
the bus masters and targets in which they are connected.
5.1.1

Priority Mechanism

The arbiters allow the bus initiators access to the AHBs using a round-robin scheme.
Table 98
AHB. The functionality of the independent arbiters is identical.
Each of the bus initiators (X, Y, and Z) is constantly requesting the bus. The bottom row
of Table 98
three masters are requesting access, X will be the winner, and then Y and Z will be
requesting. Next, Y wins the AHB and X returns with a new request. So ZX are still valid
with Z being the oldest. Next, Z wins the bus, etc.
August 2006
Order Number: 306262-004US
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IXP46X Product Line of Network Processors
illustrates a generic arbitration example for three AHB masters requesting the
lists the current bus initiator/winner of the initiators. For example, when all
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
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