Dynamically Loading Ic After Reset; Downloading Code In Ic During Program Execution - Intel IXP45X Developer's Manual

®
Intel XScale Processor—Intel
3.6.14.5

Dynamically Loading IC After Reset

An external host can load code into the instruction cache "on the fly" or "dynamically."
This occurs when the host downloads code while the processor is not being reset.
However, this requires strict synchronization between the code running on the IXP45X/
IXP46X network processors and the external host. The guidelines for downloading code
during program execution must be followed to ensure proper operation of the
processor. The description in this section focuses on using a debug handler running on
the IXP45X/IXP46X network processors to synchronize with the external host, but the
details apply for any application that is running while code is dynamically downloaded.
To dynamically download code during software debug, there must be a minimal debug
handler stub, responsible for doing the handshaking with the host, resident in the
instruction cache. This debug handler stub should be downloaded into the instruction
cache during processor reset using the method described in
on page
details for implementing the handshaking in the debug handler.
Figure 26
during dynamic code download.
Figure 26.

Downloading Code in IC During Program Execution

Debugger Actions
JTAG IR
Handler begins execution
Debug Handler Actions
The following steps describe the details for downloading code:
• Since the debug handler is responsible for synchronization during the code
download, the handler must be executing before the host can begin the download.
The debug handler execution starts when the application running on the IXP45X/
IXP46X network processors generates a debug exception or when the host
generates an external debug break.
• While the DBGTX JTAG instruction is in the JTAG IR (see
on page
• When the debug handler gets to the point where it is OK to begin the code
download, it writes to TX, which automatically sets DBG_SR[0]. This signals the
host it is OK to begin the download. The debug handler then begins polling
TXRXCTRL[31] waiting for the host to clear it through the DBGRX JTAG register (to
indicate the download is complete).
• The host writes LDIC to the JTAG IR, and downloads the code. For each line
downloaded, the host must invalidate the target line before downloading code to
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
142. "Dynamic Code Download Synchronization" on page 148
shows a high level view of the actions taken by the host and debug handler
wait for handler to signal
ready to start download
DBGTX
127), the host polls DBG_SR[0], waiting for the debug handler to set it.
download code
LDIC
signal host ready
wait for host to signal
for download
download complete
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
"Loading IC During Reset"
describes the
signal handler
download is complete
clock
15 TCKs
DBGRX
continue execution.
B4354-01
"DBGTX JTAG Command"
Developer's Manual
147