Instruction Cache Efficiency Mode; Data Cache Efficiency Mode; Common Uses Of The Pmu - Intel IXP45X Developer's Manual

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Intel XScale Processor—Intel
Table 63. Performance Monitoring Events (Sheet 2 of 2)
Event Number
(evtCountx)
0xB
0xC
0xD
0x10 through
0x17
all others
Some typical combinations of counted events are listed in this section and summarized
in Table
Table 64.

Common Uses of the PMU

Instruction Cache Efficiency
Data Cache Efficiency
Instruction Fetch Latency
Data/Bus Request Buffer Full
Stall/Writeback Statistics
Instruction TLB Efficiency
Data TLB Efficiency
Note: PMN0 and PMN1 were used for illustration purposes only. Given there are four event
counters, more elaborate combination of events could be constructed. For example,
one performance run could select 0xA, 0xB, 0xC, 0x9 events from which data cache
performance statistics could be gathered (like hit rates, number of write-backs per data
cache miss, and number of times the data cache buffers fill up per request).
3.7.4.1

Instruction Cache Efficiency Mode

PMN0 totals the number of instructions that were executed, which does not include
instructions fetched from the instruction cache that were never executed. This can
happen if a branch instruction changes the program flow; the instruction cache may
retrieve the next sequential instructions after the branch, before it receives the target
address of the branch.
PMN1 counts the number of instruction fetch requests to external memory. Each of
these requests loads 32 bytes at a time.
Statistics derived from these two events:
• Instruction cache miss-rate. This is derived by dividing PMN1 by PMN0.
• The average number of cycles it took to execute an instruction or commonly
referred to as cycles-per-instruction (CPI). CPI can be derived by dividing CCNT by
PMN0, where CCNT was used to measure total execution time.
3.7.4.2

Data Cache Efficiency Mode

PMN0 totals the number of data cache accesses, which includes cacheable and non-
cacheable accesses, mini-data cache access and accesses made to locations configured
as data RAM.
August 2006
Order Number: 306262-004US
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IXP45X and Intel IXP46X Product Line of Network Processors
Data cache miss, not including Cache Operations (defined in
on page 103)
Data cache write-back. This event occurs once for each 1/2 line (four words) that are
written back from the cache.
Software changed the PC. All 'b', 'bl', 'blx', 'mov[s] pc, Rm', 'ldm Rn, {Rx, pc}', 'ldr pc,
[Rm]', pop {pc} will be counted. An 'mcr p<cp>, 0,pc, ...', will not. The count also does not
increment when an event occurs and the PC changes to the event address, e.g., IRQ, FIQ,
SWI, etc.
Reserved.
Reserved, unpredictable results
64. In this section, we call such an event combination a mode.
Mode
0x7 (instruction count)
0xA (Dcache access)
0x1 (ICache cannot deliver)
0x8 (DBuffer stall duration)
0x2 (data stall)
0x7 (instruction count)
0xA (Dcache access)
Event Definition
EVTSEL.evtCount0
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
"Register 7: Cache Functions"
EVTSEL.evtCount1
0x0 (ICache miss)
0xB (DCache miss)
0x0 (ICache miss)
0x9 (DBuffer stall)
0xC (DCache writeback)
0x3 (ITLB miss)
0x4 (DTLB miss)
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