Memory Pipeline - Intel IXP45X Developer's Manual

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The ID unit decodes the instruction and specifies which registers are accessed in the
RFU. Based upon this information, the RFU determines if it needs to stall the pipeline
due to a register dependency. A register dependency occurs when a previous
instruction is about to modify a register value that has not been returned to the RFU
and the current instruction needs to access that same register. If no dependencies
exist, the RFU will select the appropriate data from the register file and pass it to the
next pipe stage. When a register dependency does exist, the RFU will keep track of
which register is unavailable and when the result is returned, the RFU will stop stalling
the pipe.
The Intel StrongARM architecture specifies that one of the operands for data processing
instructions as the shifter operand, where a 32-bit shift can be performed before it is
used as an input to the ALU. This shifter is located in the second half of the RF pipe
stage.
3.10.2.3.4 X1 (Execute) Pipe Stages
The X1 pipe stage performs the following functions:
• ALU calculation - the ALU performs arithmetic and logic operations, as required for
data processing instructions and load/store index calculations.
• Determine conditional instruction execution - The instruction's condition is
compared to the CPSR prior to execution of each instruction. Any instruction with a
false condition is cancelled, and will not cause any architectural state changes,
including modifications of registers, memory, and PSR.
• Branch target determination - If a branch was incorrectly predicted by the BTB, the
X1 pipe stage flushes all of the instructions in the previous pipe stages and sends
the branch target address to the BTB, which will restart the pipeline
3.10.2.3.5 X2 (Execute 2) Pipe Stages
The X2 pipe stage contains the program status registers (PSRs). This pipe stage selects
what is going to be written to the RFU in the WB cycle: PSRs (MRS instruction), ALU
output, or other items.
3.10.2.3.6 WB (Write-Back)
When an instruction has reached the write-back stage, it is considered complete.
Changes are written to the RFU.
3.10.2.4

Memory Pipeline

The memory pipeline consists of two stages, D1 and D2. The data cache unit, or DCU,
consists of the data-cache array, mini-data cache, fill buffers, and write buffers. The
memory pipeline handles load / store instructions.
3.10.2.4.1 D1 and D2 Pipe Stage
Operation begins in D1 after the X1 pipe stage has calculated the effective address for
load/stores. The data cache and mini-data cache returns the destination data in the D2
pipe stage. Before data is returned in the D2 pipe stage, sign extension and byte
alignment occurs for byte and half-word loads.
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
194
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IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale
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Processor
August 2006
Order Number: 306262-004US