Intel IXP46X Network Processors Manuals

Manuals and User Guides for Intel IXP46X Network Processors. We have 1 Intel IXP46X Network Processors manual available for free PDF download: Developer's Manual

Intel IXP46X Developer's Manual

Intel IXP46X Developer's Manual (958 pages)

Network Processors

Brand: Intel | Category: Network Hardware | Size: 8 MB

Table of Contents

Table of Contents
3
Revision History
36
1 Introduction

38
- About this Document
  38
- Intended Audience
  38
- How to Read this Document
  38
- Other Relevant Documents
  38
- Terminology and Conventions
  39
  - List of Acronyms
    39
  - Number Representation
    42
  - Signal-Naming Convention
    42
  - Register Legend
    43
2 Functional Overview

44
- IXP465 Network Processor Block Diagram
  45
- IXP460 Network Processor Block Diagram
  46
- IXP455 Network Processor Block Diagram
  47
- Key Functional Units
  48
  - Network Processor Engines (Npes)
    48
  - Internal Bus
    49
    
    North AHB
    49
    
    South AHB
    50
    
    Memory Port Interface
    50
    
    APB Bus
    51
  - MII/SMII Interfaces
    51
  - UTOPIA Level 2
    51
  - Universal Serial Bus (USB) Interfaces
    52
    
    USB 1.1 Device Interface
    52
    
    USB 2.0 Host Interface
    52
  - PCI Controller
    52
  - DDRI SDRAM Controller
    53
  - Expansion Interface
    54
  - Supported DDRI Memory Configurations
    54
  - High-Speed, Serial Interfaces
    56
  - Uarts
    56
  - Gpio
    56
  - Internal Bus Performance Monitoring Unit (IBPMU)
    57
  - Interrupt Controller
    57
  - GPIO Alternate Function Table
    57
  - Timers
    58
  - IEEE-1588 Hardware Assist
    58
  - Synchronous Serial Protocol Interface
    58
  - I2C Interface
    59
  - Aes/Des/Sha/MD-5
    59
  - Cryptography Unit
    59
  - Queue Manager
    60
- Intel Xscale ® Processor
  60
  - Super Pipeline
    62
  - Processor Block Diagram
    62
  - Bus
    62
  - Branch Target Buffer
    63
  - Instruction Memory Management Unit
    63
  - Data Memory Management Unit
    64
  - Instruction Cache
    64
  - Data Cache
    65
  - Mini-Data Cache
    65
  - Fill Buffer and Pend Buffer
    65
  - Write Buffer
    66
  - Multiply-Accumulate Coprocessor
    66
  - Performance Monitoring Unit
    66
  - Debug Unit
    67
  - Intel Xscale ® Processor
    69
  - August
    69
Memory Management Unit

69
Instruction Cache

77
- Operation When Instruction Cache Is Enabled
  77
Branch Target Buffer

83
- Branch Target Buffer (BTB) Operation
  83
  - Branch History
    84
  - BTB Entry
    84
  - Reset
    85
Data Cache

85
Configuration

96
- MRC/MCR Format
  97
- LDC/STC Format When Accessing CP14
  97
- CP15 Registers
  98
  - Register 0: ID & Cache Type Registers
    98
  - ID Register
    99
  - Cache Type Register
    99
  - Register 1: Control and Auxiliary Control Registers
    100
  - Intel ® Strongarm * Control Register
    100
  - Auxiliary Control Register
    101
  - Register 2: Translation Table Base Register
    102
  - Register 3: Domain Access Control Register
    102
  - Register 4: Reserved
    102
  - Register 5: Fault Status Register
    102
  - Translation Table Base Register
    102
  - Domain Access Control Register
    102
  - Register 6: Fault Address Register
    103
  - Register 7: Cache Functions
    103
  - Fault Status Register
    103
  - Fault Address Register
    103
  - Register 8: TLB Operations
    104
  - Cache Functions
    104
  - Register 9: Cache Lock down
    105
  - TLB Functions
    105
  - Cache Lock-Down Functions
    105
  - Data Cache Lock Register
    105
  - Register 10: TLB Lock down
    106
  - August
    106
  - Register 11-12: Reserved
    106
  - Register 13: Process ID
    106
  - TLB Lockdown Functions
    106
  - Accessing Process ID
    106
  - Process ID Register
    106
  - The PID Register Affect on Addresses
    107
  - Register 14: Breakpoint Registers
    107
  - Register 15: Coprocessor Access Register
    107
  - Accessing the Debug Registers
    107
- CP14 Registers
  108
  - Coprocessor Access Register
    108
  - Accessing the Performance Monitoring Registers
    109
  - Clock and Power Management Registers
    109
  - CP14 Registers
    109
  - Performance Monitoring Registers
    109
  - Accessing the Debug Registers
    110
  - CCLKCFG Register
    110
  - Clock and Power Management
    110
  - PWRMODE Register
    110
  - Software Debug Registers
    110
Software Debug

111
- Definitions
  111
- Debug Registers
  111
- Debug Modes
  112
  - Halt Mode
    112
  - Monitor Mode
    112
- Debug Control and Status Register (DCSR)
  112
  - Global Enable Bit (GE)
    114
  - Halt Mode Bit (H)
    114
  - Vector Trap Bits (TF,TI,TD,TA,TS,TU,TR)
    114
  - Sticky Abort Bit (SA)
    114
  - Method of Entry Bits (MOE)
    114
  - Trace Buffer Mode Bit (M)
    114
  - Trace Buffer Enable Bit (E)
    114
- Debug Exceptions
  115
  - Halt Mode
    115
  - Event Priority
    115
  - Monitor Mode
    117
- HW Breakpoint Resources
  117
- Software Breakpoints
  120
- Transmit/Receive Control Register
  120
  - RX Register Ready Bit (RR)
    121
  - TX RX Control Register (TXRXCTRL)
    121
  - Normal RX Handshaking
    121
  - Overflow Flag (OV)
    122
  - Download Flag (D)
    122
  - High-Speed Download Handshaking States
    122
  - TX Register Ready Bit (TR)
    123
  - Conditional Execution Using TXRXCTRL
    123
  - TX Handshaking
    123
  - TXRXCTRL Mnemonic Extensions
    123
  - TX Register
    123
- Transmit Register
  124
- Receive Register
  124
- Debug JTAG Access
  124
  - RX Register
    124
  - SELDCSR Hardware
    125
  - SELDCSR JTAG Command
    125
  - SELDCSR JTAG Register
    125
  - SELDCSR Data Register
    126
  - DBGTX JTAG Command
    127
  - DBGTX JTAG Register
    127
  - DBGRX JTAG Command
    128
  - DBGRX JTAG Register
    128
  - DBGTX Hardware
    128
  - DBGRX Hardware
    129
  - Rx Write Logic
    130
  - DBGRX Data Register
    131
  - Debug JTAG Data Register Reset Values
    132
- Trace Buffer
  132
  - Trace Buffer CP Registers
    132
  - DEBUG Data Register Reset Values
    132
  - CP 14 Trace Buffer Register Summary
    133
  - Checkpoint Register (Chkptx)
    133
- Trace Buffer Entries
  134
  - Message Byte
    134
  - Message Byte Formats
    134
  - TBREG Format
    134
  - Message Byte Formats
    135
  - Trace Buffer Usage
    137
  - Indirect Branch Entry Address Byte Organization
    137
  - High-Level View of Trace Buffer
    137
- Downloading Code in Icache
  139
- Halt Mode Software Protocol
  150
  - Starting a Debug Session
    150
  - Implementing a Debug Handler
    152
  - Ending a Debug Session
    155
  - Debug Handler Code: Download Bit and Overflow Flag
    155
- Software Debug Notes and Errata
  156
Performance Monitoring

157
- Overview
  157
- Performance Monitoring Registers
  157
- Register Description
  158
  - Clock Counter (CCNT)
    158
  - Performance Count Registers
    158
  - Clock Count Register (CCNT)
    158
  - Performance Monitor Count Register (PMN0 - PMN3)
    158
  - Register Legend
    158
  - Performance Monitor Control Register
    159
  - Interrupt Enable Register
    159
  - Overflow Flag Status Register
    160
  - Event Select Register
    161
- Managing the Performance Monitor
  162
- Performance Monitoring Events
  162
  - Instruction Cache Efficiency Mode
    163
  - Data Cache Efficiency Mode
    163
  - Common Uses of the PMU
    163
  - Instruction Fetch Latency Mode
    164
  - Data/Bus Request Buffer Full Mode
    164
  - Stall/Write-Back Statistics
    165
  - August
    165
  - Instruction TLB Efficiency Mode
    165
  - Data TLB Efficiency Mode
    165
- Multiple Performance Monitoring Run Statistics
  166
- Examples
  166
Programming Model

167
Intel Strongarm Architecture Compatibility

167
Intel Strongarm Architecture Implementation Options

168
- Big-Endian Versus Little-Endian
  168
- 26-Bit Architecture
  168
- Thumb
  168
- Base Register Update
  169
- Strongarm * DSP-Enhanced Instruction Set
  169
- Architecture
  169
  - August
    169
  - DSP Coprocessor 0 (CP0)
    169
  - Multiply with Internal Accumulate Format
    170
  - Miaph{<Cond>} Acc0, Rm, Rs
    171
  - Mia{<Cond>} Acc0, Rm, Rs
    171
  - Miaxy{<Cond>} Acc0, Rm, Rs
    172
  - Internal Accumulator Access Format
    173
  - Mar{<Cond>} Acc0, Rdlo, Rdhi
    174
  - Mra{<Cond>} Rdlo, Rdhi, Acc0
    174
  - First-Level Descriptors
    175
  - New
    175
  - Second-Level Descriptors for Coarse
    175
  - Additions to CP15 Functionality
    176
  - Second-Level Descriptors for Fine
    176
  - Event Architecture
    177
  - Event Priority
    177
  - Exception Summary
    177
  - Processors': Encoding of Fault Status for Prefetch Aborts
    178
  - Events from Preload Instructions
    180
Performance Considerations

181
- Interrupt Latency
  181
- Branch Prediction
  182
- Addressing Modes
  182
- Instruction Latencies
  182
Optimization Guide

189
- Introduction
  189
- Processor Pipeline
  190
  - General Pipeline Characteristics
    190
  - RISC Super-Pipeline
    191
  - Pipelines and Pipe Stages
    191
  - Instruction Flow through the Pipeline
    192
  - Main Execution Pipeline
    193
  - Memory Pipeline
    194
  - Multiply/Multiply Accumulate (MAC) Pipeline
    195
- Basic Optimizations
  195
  - Conditional Instructions
    195
  - Bit Field Manipulation
    199
  - Optimizing the Use of Immediate Values
    200
  - Optimizing Integer Multiply and Divide
    200
  - Effective Use of Addressing Modes
    201
- Cache and Prefetch Optimizations
  201
  - Instruction Cache
    201
  - Data and Mini Cache
    203
  - Data Alignment
    205
  - Cache Considerations
    206
  - Prefetch Considerations
    207
- Instruction Scheduling
  212
  - Scheduling Loads
    212
  - Scheduling Data Processing Instructions
    216
  - Scheduling Multiply Instructions
    217
  - Scheduling SWP and SWPB Instructions
    218
    
    Scheduling the MRA and MAR Instructions (MRRC/MCRR)
    218
    
    Scheduling the MIA and MIAPH Instructions
    219
    
    Scheduling MRS and MSR Instructions
    219
    
    Scheduling CP15 Coprocessor Instructions
    220
  - Optimizing C Libraries
    220
  - Optimizations for Size
    220
    
    Space/Performance Trade off
    220
4 Network Processor Engines (NPE)

222
- Processors: Network Processor Functions
  222
5 Internal Buses

224
- Internal Bus Arbiters
  225
  - Priority Mechanism
    225
- Memory Map
  226
- Bus Arbitration Example: Three Requesting Masters
  226
6 Ethernet Macs

229
- Multiple Ethernet PHYS Connected to Processor
  229
- Ethernet Coprocessor
  230
  - Ethernet Coprocessor APB Interface
    230
  - Ethernet Coprocessor NPE Interface
    230
  - Ethernet Coprocessor Interface
    230
  - Ethernet Coprocessor MDIO Interface
    231
  - MDIO Write
    232
  - Transmitting Ethernet Frames with MII Interfaces
    233
  - MDIO Read
    233
  - Receiving Ethernet Frames with MII Interfaces
    236
  - General Ethernet Coprocessor Configuration
    238
- Register Descriptions Ethernet Macs
  239
  - Ethernet MAC 0 on NPE B
    240
  - Register Legend
    240
  - Ethernet MAC 1 on NPE B
    241
  - Ethernet MAC 2 on NPE B
    243
  - Ethernet MAC 2 on NPE B
    244
  - Ethernet MAC on NPE a
    246
  - Ethernet MAC on NPE C
    247
  - Transmit Control 1
    249
  - Transmit Control 2
    249
  - Receive Control 1
    250
  - Receive Control 2
    251
  - Random Seed
    251
  - Threshold for Partially Empty
    251
  - Threshold for Partially Full
    252
  - Buffer Size for Transmit
    252
  - Transmit Deferral Parameter
    253
  - Receive Deferral Parameter
    253
  - Transmit Two Part Deferral Parameters 1
    253
  - Transmit Two Part Deferral Parameters 2
    254
  - Slot Time
    254
  - MDIO Commands Registers
    254
  - MDIO Command 1
    255
  - MDIO Command 2
    255
  - MDIO Command 3
    255
  - MDIO Command 4
    256
  - MDIO Status Registers
    256
  - MDIO Status 1
    256
  - MDIO Status 2
    257
  - MDIO Status 3
    257
  - MDIO Status 4
    257
  - Address Mask Registers
    257
  - Address Mask 1
    258
  - Address Mask 2
    258
  - August
    258
  - Address Mask 3
    259
  - Address Mask 4
    259
  - Address Mask 5
    259
  - Address Mask 6
    260
  - Address Registers
    260
  - Address 1
    261
  - Address 2
    261
  - Address 3
    261
  - Address 4
    262
  - Address 5
    262
  - Address 6
    262
  - Threshold for Internal Clock
    263
  - Unicast Address Registers
    263
  - Unicast Address 1
    264
  - Unicast Address 2
    264
  - Unicast Address 3
    264
  - Unicast Address 4
    264
  - Unicast Address 5
    265
  - Unicast Address 6
    265
  - Core Control
    265
  - August 2006 Developer's Manual
    267
7 UTOPIA Level 2

268
- Introduction
  268
- UTOPIA Transmit Module
  269
- UTOPIA Level 2 Coprocessor
  269
- UTOPIA Level 2 MPHY Transmit Polling
  271
- UTOPIA Receive Module
  272
- UTOPIA Level 2 MPHY Receive Polling
  274
- UTOPIA Level 2 Coprocessor / NPE Coprocessor: Bus Interface
  275
- MPHY Polling Routines
  275
- UTOPIA Level 2 Clocks
  276
8 USB 1.1 Device Controller

278
- USB Overview
  278
- Device Configuration
  279
- USB Operation
  280
  - Signalling Levels
    280
  - Endpoint Configuration: Universal Serial Bus Device Controller
    280
  - Bit Encoding
    281
  - USB States
    281
  - Field Formats
    282
  - NRZI Bit Encoding Example
    282
  - Packet Formats
    283
    
    Endpoint Field Addressing
    283
    
    Data Packet Type
    284
    
    IN, OUT, and SETUP Token Packet Format
    284
    
    SOF Token Packet Format
    284
    
    Start-Of-Frame Packet Type
    284
    
    Token Packet Type
    284
    
    Handshake Packet Type
    285
  - Transaction Formats
    285
    
    Bulk Transaction Type
    285
    
    Handshake Packet Format
    285
    
    Isochronous Transaction Type
    286
    
    Control Transaction Type
    286
    
    Bulk Transaction Formats
    286
    
    Isochronous Transaction Formats
    286
    
    Control Transaction Formats
    286
    
    Interrupt Transaction Type
    287
  - UDC Device Requests
    287
  - Interrupt Transaction Formats
    287
  - UDC Configuration
    288
- UDC Hardware Connections
  289
  - Self-Powered Device
    289
  - Bus-Powered Devices
    289
- Register Descriptions
  289
  - Register Legend
    290
  - UDC Control Register
    291
    
    UDC Enable
    291
    
    UDC Active
    292
    
    UDC Resume (RSM)
    292
- Resume Interrupt Request (RESIR)
  292
- Suspend Interrupt Request (SUSIR)
  292
- Suspend/Resume Interrupt Mask (SRM)
  292
- Reset Interrupt Request (RSTIR)
  292
- Reset Interrupt Mask (REM)
  292
UDC Endpoint 0 Control/Status Register

293
- OUT Packet Ready (OPR)
  294
- Flush Tx FIFO (FTF)
  294
  - IN Packet Ready (IPR)
    294
  - Device Remote Wake-Up Feature (DRWF)
    294
  - Sent Stall (SST)
    294
- Force Stall (FST)
  295
- Receive FIFO Not Empty (RNE)
  295
- Setup Active (SA)
  295
UDC Endpoint 1 Control/Status Register

296
- Transmit FIFO Service (TFS)
  296
- Transmit Packet Complete (TPC)
  296
- Flush Tx FIFO (FTF)
  296
- Transmit Underrun (TUR)
  296
- Sent STALL (SST)
  297
  - Force STALL (FST)
    297
  - Bit 6 Reserved
    297
- Transmit Short Packet (TSP)
  297
UDC Endpoint 2 Control/Status Register

298
- Receive FIFO Service (RFS)
  298
- Receive Packet Complete (RPC)
  298
- Bit 2 Reserved
  298
- Sent Stall (SST)
  299
- Force Stall (FST)
  299
- Receive FIFO Not Empty (RNE)
  299
- Receive Short Packet (RSP)
  299
UDC Endpoint 3 Control/Status Register

300
- Transmit FIFO Service (TFS)
  300
- Transmit Packet Complete (TPC)
  301
- Flush Tx FIFO (FTF)
  301
  - Transmit Underrun (TUR)
    301
  - Bit 4 Reserved
    301
- Bit 5 Reserved
  301
- Bit 6 Reserved
  301
- Transmit Short Packet (TSP)
  301
UDC Endpoint 4 Control/Status Register

302
- Receive FIFO Service (RFS)
  302
- Receive Packet Complete (RPC)
  303
- Receive Overflow (ROF)
  303
- Receive FIFO Not Empty (RNE)
  303
  - Bit 3 Reserved
    303
- Bit 4 Reserved
  303
- Bit 5 Reserved
  303
  - Receive Short Packet (RSP)
    303
UDC Endpoint 5 Control/Status Register

304
- Transmit FIFO Service (TFS)
  304
- August
  304
- Flush Tx FIFO (FTF)
  305
  - Transmit Packet Complete (TPC)
    305
  - Transmit Underrun (TUR)
    305
  - Sent STALL (SST)
    305
- Force STALL (FST)
  305
- Bit 6 Reserved
  306
- Transmit Short Packet (TSP)
  306
- Sent Stall (SST)
  320
- Force Stall (FST)
  320
- Receive FIFO Not Empty (RNE)
  320
- Receive Short Packet (RSP)
  321
- UDC Endpoint 13 Control/Status Register
  321
- Transmit FIFO Service (TFS)
  322
- Transmit Packet Complete (TPC)
  322
- Flush Tx FIFO (FTF)
  322
- Bit 4 Reserved
  322
- Bit 5 Reserved
  322
- Bit 6 Reserved
  322
- Transmit Short Packet (TSP)
  322
- UDC Endpoint 14 Control/Status Register
  323
- Receive FIFO Service (RFS)
  323
- Receive Packet Complete (RPC)
  324
- Receive Overflow (ROF)
  324
- Bit 3 Reserved
  324
- Bit 4 Reserved
  324
- Bit 5 Reserved
  324
- Receive FIFO Not Empty (RNE)
  324
- Receive Short Packet (RSP)
  324
- UDC Endpoint 15 Control/Status Register
  325
- Transmit FIFO Service (TFS)
  325
- Transmit Packet Complete (TPC)
  326
- Flush Tx FIFO (FTF)
  326
- Transmit Underrun (TUR)
  326
- Sent STALL (SST)
  326
- Force STALL (FST)
  326
- Bit 6 Reserved
  327
- Transmit Short Packet (TSP)
  327
- UDC Interrupt Control Register 0
  328
- Interrupt Mask Endpoint X (IMX), Where X Is 0 through 7
  328
- UDC Interrupt Control Register 1
  329
- Interrupt Mask Endpoint X (IMX), Where X Is 8 through 15
  329
- UDC Status/Interrupt Register 0
  330
- Endpoint 0 Interrupt Request (IR0)
  330
- Endpoint 1 Interrupt Request (IR1)
  331
- Endpoint 2 Interrupt Request (IR2)
  331
- Endpoint 3 Interrupt Request (IR3)
  331
- Endpoint 4 Interrupt Request (IR4)
  331
- Endpoint 5 Interrupt Request (IR5)
  331
- Endpoint 6 Interrupt Request (IR6)
  331
- Endpoint 7 Interrupt Request (IR7)
  331
- UDC Status/Interrupt Register 1
  332
- Endpoint 8 Interrupt Request (IR8)
  332
- Endpoint 9 Interrupt Request (IR9)
  332
- Endpoint 10 Interrupt Request (IR10)
  333
- Endpoint 11 Interrupt Request (IR11)
  333
- Endpoint 12 Interrupt Request (IR12)
  333
- Endpoint 13 Interrupt Request (IR13)
  333
- Endpoint 14 Interrupt Request (IR14)
  333
- Endpoint 15 Interrupt Request (IR15)
  333
- UDC Frame Number High Register
  334
- UDC Frame Number MSB (FNMSB)
  334
- August
  335
- Isochronous Packet Error Endpoint 4 (IPE4)
  335
- Isochronous Packet Error Endpoint 9 (IPE9)
  335
- Isochronous Packet Error Endpoint 14 (IPE14)
  335
- Start of Frame Interrupt Mask (SIM)
  335
- Start of Frame Interrupt Request (SIR)
  335
- UDC Frame Number Low Register
  336
- UDC Byte Count Register 2
  337
- Endpoint 2 Byte Count (BC[7:0])
  337
- UDC Byte Count Register 4
  338
- Endpoint 4 Byte Count (BC[7:0])
  338
- UDC Byte Count Register 7
  338
- Endpoint 7 Byte Count (BC[7:0])
  339
- UDC Byte Count Register 9
  339
- Endpoint 9 Byte Count (BC[7:0])
  339
- UDC Byte Count Register 12
  340
- Endpoint 12 Byte Count (BC[7:0])
  340
- UDC Byte Count Register 14
  341
- Endpoint 14 Byte Count (BC[7:0])
  341
- UDC Endpoint 0 Data Register
  341
- UDC Data Register 1
  342
- UDC Data Register 2
  343
- UDC Data Register 3
  343
- UDC Data Register 4
  344
- UDC Data Register 5
  345
- UDC Data Register 6
  345
- UDC Data Register 7
  346
- UDC Data Register 8
  346
- UDC Data Register 9
  347
- UDC Data Register 10
  348
- UDC Data Register 11
  348
- UDC Data Register 12
  349
- UDC Data Register 13
  349
- UDC Data Register 14
  350
- UDC Data Register 15
  351
- USB 2.0 Host Controller
  352
- Overview
  352
- Usb
  352
- Usb 2.0
  353
- Feature List
  354
- Example USB 2.0 System Configuration
  354
- Block Diagram
  355
- Theory of Operation
  355
- Software Model
  355
- Host Data Structure
  355
- Top-Level Block Diagram
  355
- Hardware Model
  358
- Block Diagram
  358
- Microprocessor Interface
  359
- Microprocessor Interface Block Diagram
  359
- DMA Engine
  360
- DMA Engine Block Diagram
  360
- Dual Port RAM Controller
  361
- Protocol Engine
  361
- Protocol Engine Block Diagram
  361
- Port Controller
  362
- Port Controller Block Diagram
  362
- System Bus Interface
  363
- System Level Issues and Core Configuration
  363
- Configuration Constants
  363
- Configuration Controls
  363
- Detailed Register Descriptions
  364
- Register Legend
  364
- Interface Register Sets
  365
- Register Legend
  365
- Configuration, Control and Status Register Set
  366
- Host Capability Registers
  366
- Identification Registers
  367
- Hwgeneral
  367
- Identification Register Fields
  367
- Hwhost
  368
- Hwdevice
  368
- Hwtxbuf
  369
- Hwrxbuf
  369
- Host Capability Registers
  370
- CAPLENGTH - EHCI Compliant
  370
- HCIVERSION - EHCI Compliant
  370
- HCSPARAMS - EHCI Compliant with Extensions
  370
- HCCPARAMS - EHCI Compliant
  371
- Reserved Register #1
  372
- DCCPARAMS (Non-EHCI)
  372
- DCCPARAMS - Device Control Capability Parameters
  373
- Host Operational Registers
  373
- Usbcmd
  373
- August
  374
- Usbsts
  375
- USBSTS - USB Status
  376
- Usbintr
  377
- USBINTR - USB Interrupt Enable
  377
- Frindex
  378
- Ctrldssegment
  379
- Periodiclistbase
  379
- Host Controller (PERIODICLISTBASE)
  379
- Asynclistaddr; Endpointlistaddr
  380
- Host Controller (ASYNCLISTADDR)
  380
- Burstsize
  380
- PERIODICLISTBASE - Host Controller Frame List Base Address
  380
- Txfilltuning
  381
- 10Configflag
  381
- BURSTSIZE - Host Controller Embedded TT Async. Buffer Status
  381
- 11Portscx
  382
- 1Host Controller
  382
- Portscx - Port Status Control[1:8]
  383
- 12Usbmode
  387
- USBMODE - USB Device Mode
  387
- Host Data Structures
  387
- Periodic Frame List
  388
- Typ Field Value Definitions
  389
- Asynchronous List Queue Head Pointer
  390
- Periodic Schedule Organization
  390
- Isochronous (High-Speed) Transfer Descriptor (Itd)
  391
- Asynchronous Schedule Organization
  391
- Next Link Pointer
  392
- Isochronous Transaction Descriptor (Itd)
  392
- Next Schedule Element Pointer
  393
- Itd Transaction Status and Control List
  393
- Itd Transaction Status and Control
  393
- Itd Buffer Page Pointer List (Plus)
  394
- Itd Buffer Pointer Page 0 (Plus)
  394
- Itd Buffer Pointer Page 1 (Plus)
  394
- Split Transaction Isochronous Transfer Descriptor (Sitd)
  395
- Next Link Pointer
  395
- Split-Transaction Isochronous Transaction Descriptor (Sitd)
  395
- Itd Buffer Pointer Page 2 (Plus)
  395
- Itd Buffer Pointer
  395
- Endpoint and Transaction Translator Characteristics
  396
- Sitd Endpoint Capabilities/Characteristics
  396
- Micro-Frame Schedule Control
  397
- Sitd Transfer State
  397
- Sitd Transfer Status and Control
  397
- Sitd Buffer Pointer List (Plus)
  398
- Sitd Back Link Pointer
  398
- Queue Element Transfer Descriptor (Qtd)
  399
- Queue Element Transfer Descriptor Block Diagram
  399
- Sitd Back Link Pointer
  399
  - Qtd Next Element Transfer Pointer (Dword 0)
    400
  - Qtd Alternate Next Element Transfer Pointer (Dword 1)
    400
- Next Qtd Pointer
  400
- Alternate Next Qtd Pointer
  400
- Qtd Token
  400
- Qtd Token (Dword 2)
  401
- Qtd Buffer Page Pointer List
  403
- Qtd Buffer Pointer(S) (Dwords 3-7)
  403
- Queue Head
  404
- Queue Head Horizontal Link Pointer
  404
- Queue Head Structure Layout
  404
- Endpoint Capabilities/Characteristics
  405
- Endpoint Characteristics: Queue Head Dword 1
  405
- Endpoint Capabilities: Queue Head Dword 2
  406
- Transfer Overlay
  407
- Current Qtd Link Pointer
  407
- Periodic Frame Span Traversal Node (FSTN)
  408
- FSTN Normal Path Pointer
  408
- Frame Span Traversal Node Structure Layout
  408
- Host-Controller Rules for Bits in Overlay (Dwords 5, 6, 8 and 9)
  408
- FSTN Back Path Link Pointer
  409
- Host Operational Model
  409
- FSTN Normal Path Pointer Signals
  409
- FSTN Back Path Link Pointer Signals
  409
- Host Controller Initialization
  410
- Default Values of Operational Register Space
  410
- Port Routing and Control
  411
- Example USB 2.0 Host Controller Port Routing Block Diagram
  411
- Port Routing Control Via EHCI Configured (CF) Bit
  412
- August
  412
- Port Routing Control Via Portowner and Disconnect Event
  413
- Example Port Routing State Machine
  414
- Port Owner Hand-Off State Machine
  414
- Port Power
  415
- Port Reporting Over-Current
  415
- Port Power Enable Control Rules
  415
- Suspend/Resume
  416
- Port Suspend/Resume
  416
- Schedule Traversal Rules
  418
- Behavior During Wake-Up Events
  418
- Derivation of Pointer into Frame List Array
  419
- General Format of Asynchronous Schedule List
  419
- Example: Preserving Micro-Frame Integrity
  420
- Best Fit Approximation
  421
- Example Worst-Case Transaction Timing Components
  421
- Periodic Schedule Frame Boundaries Versus Bus Frame Boundaries
  423
- Frame Boundary Relationship between HS Bus and FS/LS Bus
  423
- Relationship of Periodic Schedule Frame Boundaries to Bus Frame Boundaries
  424
- Operation of FRINDEX and SOFV (SOF Value Register)
  424
- Periodic Schedule
  425
- Managing Isochronous Transfers Using Itds
  426
- Host Controller Operational Model for Itds
  426
- Example Periodic Schedule
  426
- Software Operational Model for Itds
  428
- Example Association of Itds to Client Request Buffer
  429
- Asynchronous Schedule
  430
- Adding Queue Heads to Asynchronous Schedule
  431
- Removing Queue Heads from Asynchronous Schedule
  432
- Generic Queue Head Unlink Scenario
  434
- Empty Asynchronous Schedule Detection
  435
- Restarting Asynchronous Schedule before EOF
  435
- Asynchronous Schedule List with Annotation to Mark Head of List
  435
- Example State Machine for Managing Asynchronous Schedule Traversal
  436
- Asynchronous Schedule State Machine Transition Actions
  437
- Typical Low- /Full-Speed Transaction Times
  437
- Asynchronous Schedule Traversal: Start Event
  438
- Reclamation Status Bit (USBSTS Register)
  438
- Operational Model for Nak Counter
  439
- Nakcnt Field Adjustment Rules
  439
- Nak Count Reload Control
  440
- Example HC State Machine for Controlling Nak Counter Reloads
  440
- 10Managing Control/Bulk/Interrupt Transfers Via Queue Heads
  441
- Host Controller Queue Head Traversal State Machine
  442
- 1Fetch Queue Head
  443
- 2Advance Queue
  443
- 3Execute Transaction
  444
- Actions for Park Mode, Based on Endpoint Response and Residual Transfer State
  448
- 4Write Back Qtd
  449
- 5Follow Queue Head Horizontal Pointer
  449
- 6Buffer Pointer List Use for Data Streaming with Qtds
  449
- Example Mapping of Qtd Buffer Pointers to Buffer
  450
- 7Adding Interrupt Queue Heads to the Periodic Schedule
  451
- 8Managing Transfer Complete Interrupts from Queue Heads
  451
- Example Periodic Reference Patterns for Interrupt Transfers with 2-Ms Poll Rate
  451
- 11Ping Control
  452
- Ping Control State Transition Table
  452
- Ping State Encoding
  452
- 12Split Transactions
  453
- 1Split Transactions for Asynchronous Transfers
  453
- Host Controller Asynchronous Schedule Split-Transaction State Machine
  454
- 2Split Transaction Interrupt
  455
- Split Transaction, Interrupt Scheduling Boundary Conditions
  456
- General Structure of EHCI Periodic Schedule Utilizing Interrupt Spreading
  457
- Host Controller Operational Model for Fstns
  458
- Example Host Controller Traversal of Recovery Path Via Fstns
  459
- Software Operational Model for Fstns
  460
- Split Transaction State Machine for Interrupt
  463
- Interrupt IN/OUT Do Complete Split State Execution Criteria
  467
- 3Split Transaction Isochronous
  468
- Split Transaction, Isochronous Scheduling Boundary Conditions
  469
- Sitd Scheduling Boundary Examples
  471
- Split Transaction State Machine for Isochronous
  474
- Initial Conditions for out Sitd's TP and T-Count Fields
  475
- Transaction Position (Tp)/Transaction Count (T-Count) Transition Table
  475
  - Summary Sitd Split Transaction State
    478
  - Example Case 2A - Software Scheduling Sitds for an in Endpoint
    480
- 13Host Controller Pause
  481
- 14Port Test Modes
  481
- 15Interrupts
  482
- Summary of Transaction Errors
  483
- 1Transfer/Transaction Based Interrupts
  483
- Data Buffer Error
  484
- 2Host Controller Event Interrupts
  485
- EHCI Deviation
  486
- Embedded Transaction Translator Function
  486
- Summary Behavior of EHCI Host Controller on Host System Errors
  486
- Capability Registers
  487
- Operational Registers
  487
- Discovery
  487
- Standard EHCI Vs. EHCI with Embedded Transaction Translator
  487
- Data Structures
  488
- Operational Model
  488
- Condition Vs. Emulate TT Response
  489
- Device Operation
  490
- USBMODE Register
  490
- EHCI Reserved Fields
  490
- SOF Interrupt
  491
- Embedded Design Interface
  491
- Frame Adjust Register
  491
- Miscellaneous Variations from EHCI
  491
- Programmable Physical Interface Behavior
  491
- Discovery
  491
- Port Test Mode
  492
- Usb Power States
  493
- Host Power States
  493
  - PCI Controller
    495
  - Introduction
    495
- PCI Bus Configured as a Host
  496
- PCI Bus Configured as an Option
  496
- PCI Controller Block Diagram
  497
- PCI Target Interface Supported Commands
  498
- PCI Initiator Interface Supported Commands
  499
- List of Features
  500
- PCI Controller Configured as Host
  501
- Type 0 Configuration Address Phase
  502
- Type 1 Configuration Address Phase
  502
- Example: Generating a PCI Configuration Write and Read
  503
- PCI Controller Configured as Option
  504
- PCI Memory Map Allocation
  508
- Initializing the PCI Controller Configuration Registers
  509
- PCI Byte Enables Using CRP Access Method
  511
- PCI Configuration Space
  511
- PCI Controller South AHB Transactions
  512
- PCI Controller Functioning as Bus Initiator
  512
- Command Type for PCI Controller Configuration and Status Register Accesses
  512
- Initiated PCI Type-0 Configuration Read Cycle
  513
- Initiated Type-0 Read Transaction
  513
- Initiated Type-0 Write Transaction
  513
- Initiated PCI Type-0 Configuration Write Cycle
  514
- Initiated Type-1 Read Transaction
  514
- Initiated PCI Type-1 Configuration Read Cycle
  515
- Initiated Type-1 Write Transaction
  515
- Initiated PCI Type-1 Configuration Write Cycle
  516
- Initiated PCI Memory Read Cycle
  516
- Initiated Memory Read Transaction
  516
- Initiated PCI Memory Write Cycle
  517
- Initiated Memory Write Transaction
  517
- Initiated I/O Read Transaction
  517
- Initiated PCI I/O Read Cycle
  518
- Initiated I/O Write Transaction
  518
- Initiated PCI I/O Write Cycle
  519
- Initiated Burst Memory Read Transaction
  519
- Initiated PCI Burst Memory Read Cycle
  520
- Initiated Burst Memory Write Transaction
  520
- PCI Controller Functioning as Bus Target
  521
- PCI Controller Door Bell Register
  521
- Initiated PCI Burst Memory Write Cycle
  521
- Functional Description
  522
- Pci Byte-Enable Generation
  522
- Pci Core
  522
- PCI Target Interface Supported Commands
  523
- Pci Initiator Interface
  524
- PCI Initiator Interface Supported Commands
  525
- PCI Host Functions
  526
- PCI Controller Arbiter Configuration
  527
- PCI CLOCK and RESET Sourcing
  528
- Pci Controller Clock and Reset Generation
  528
- Pci Configuration Register Access
  528
- Pci Pad Drive Strength Compensation Support
  529
- Ahb Master Interface
  530
- PCI-To-AHB Address Translation
  531
- Ahb Master Writes
  531
- Ahb Master Reads
  532
- Ahb Slave Interface
  532
- AHB-To-PCI Address Translation - Memory Cycles
  533
- Pci Byte Enable Generation
  535
- PCI Controller DMA
  536
- PCI Byte Enables for Sub-Word Single AHB Read/Write Cycles
  536
- AHB-To-PCI DMA-Transfer Byte Lane Swapping
  538
- PCI-To-AHB DMA-Transfer Byte Lane Swapping
  538
- Ahb-To-Pci Dma Channel Operation
  540
- Pci-To-Ahb Dma Channel Operation
  540
- Data Byte Alignment and Addressing — Pci Endianness
  541
- Byte Lane Routing During PCI Target Accesses of the AHB Bus - Big-Endian AHB Bus
  542
- Byte Lane Routing During PCI Target Accesses of the AHB Bus - Little-Endian AHB Bus
  543
- Byte Lane Routing During AHB Slave Accesses of the PCI Bus
  544
- Big-Endian AHB Bus
  544
- Byte Lane Routing During AHB Slave Accesses of the PCI Bus
  545
- Little-Endian AHB Bus
  545
- Byte Lane Routing During DMA Transfers
  546
- PCI Controller Interrupts
  547
- Byte Lane Routing During CSR Accesses
  547
- Pci Interrupt Generation
  547
- Internal Interrupt Generation
  548
- PCI RCOMP Circuitry
  549
  - August
    549
  - Register Descriptions
    549
- PCI Configuration Registers
  549
- Register Legend
  549
- PCI Configuration Register Descriptions
  550
- PCI Configuration Register Map
  550
- Device ID/Vendor ID Register
  550
- Status Register/Control Register
  551
- Class Code/Revision ID Register
  552
- Bist/Header Type/Latency Timer/Cache Line Register
  553
- Base Address 0 Register
  553
- Base Address 1 Register
  554
- Base Address 2 Register
  554
- Base Address 3 Register
  555
- Base Address 4 Register
  555
- Base Address 5 Register
  556
- Subsystem ID/Subsystem Vendor ID Register
  556
- Max_Lat, Min_Gnt, Interrupt Pin, and Interrupt Line Register
  557
- Retry Timeout/Trdy Timeout Register
  557
- CSR Address Map
  558
- Pci Controller Configuration and Status Registers (Csrs)
  558
- PCI Controller Non-Prefetch Address Register
  559
- PCI Controller Non-Prefetch Command/Byte Enables Register
  559
- PCI Controller Non-Prefetch Write Data Register
  560
- Pci Controller Non-Prefetch Read Data Register
  560
- Pci Controller Configuration Port Address/Command/Byte
  561
- Enables Register
  561
- Pci Controller Configuration Port Write Data Register
  562
- Pci Controller Configuration Port Read Data Register
  562
- Pci Controller Control and Status Register
  563
- PCI Controller Interrupt Status Register
  564
- Dma Control Register
  565
- Pci Controller Interrupt Enable Register
  565
- Ahb Memory Base Address Register
  566
- Ahb I/O Base Address Register
  567
- Pci Memory Base Address Register
  567
- Ahb Doorbell Register
  568
- PCI Doorbell Register
  569
- AHB-To-PCI DMA AHB Address Register 0
  569
- AHB-To-PCI DMA AHB Address Register 1
  571
- AHB-To-PCI DMA PCI Address Register 1
  571
- PCI-To-AHB DMA PCI Address Register 0
  573
- PCI-To-AHB DMA Length Register 0
  573
- PCI-To-AHB DMA Length Register 1
  575
- Error/Abnormal Conditions
  575
- Error Handling as a PCI Target
  575
- Error Handling as a PCI Initiator During PCI Direct Access from the AHB Bus
  577
- Error Handling as a PCI Initiator During Non-Prefetch Operations
  578
- Error Handling During PCI-To-AHB DMA Channel Operations
  578
- Error Handling During AHB-To-PCI DMA Channel Operations
  579
- Memory Controller
  581
- Functional Blocks
  582
- Memory Controller Block Diagram
  584
- Transaction Ports
  584
- Address Decode Blocks
  585
- Configuration Registers
  586
- Memory Transaction Queues
  586
- Refresh Counter
  586
- DDRI SDRAM Memory Support
  587
- Ddri Sdram Control Block
  587
- Ddri Sdram Rcomp Block
  587
- DDRI SDRAM Memory Configuration Options
  588
- Ddri Sdram Interface
  588
- Dual-Bank DDRI SDRAM Memory Subsystem
  589
- Supported DDRI SDRAM Configurations
  590
- Ddri Sdram Bank Sizes and Configurations
  590
- DDRI SDRAM Address Register Summary
  591
- DDRI SDRAM Address Translation for 128/512 Mbit (X16/X8), 1 Gbitx8
  593
- And 256 Mbitx8 Devices
  593
- DDRI SDRAM Address Translation for 256 Mbitx16 Devices
  593
- Mtctr Register Setup
  593
- Ddri Sdram Addressing
  593
- Bit to 32-Bit Addressing
  594
- DDRI SDRAM Address Translation for 1 Gbitx16 Devices
  594
- Bit Data Bus Width
  594
- Page Hit/Miss Determination
  595
  - Page Hit/Miss Logic for 128/256/512/1, 024-Bit Mode
    596
  - Logical Memory Image of a DDRI SDRAM Memory Subsystem
    597
- DDRI SDRAM Commands
  598
- Ddri Sdram Initialization
  598
- Supported DDRI SDRAM Extended Mode Register Settings
  599
- Supported DDRI SDRAM Mode Register Settings
  600
- DDRI SDRAM Initialization Sequence (Controlled with Software)
  601
- Ddri Sdram Mode Programming
  602
- DDRI SDRAM Pipelined Reads
  606
- Ddri Sdram Read Cycle
  606
- DDRI SDRAM Read, 36 Bytes, ECC Enabled, BL=4
  607
- Ddri Sdram Write Cycle
  609
- DDRI SDRAM Write, 36 Bytes, ECC Enabled, BL=4
  610
- DDRI SDRAM Pipelined Writes
  612
- Ddri Sdram Refresh Cycle
  612
- Refresh While the Memory Bus Is Not Busy
  613
- Typical Refresh Frequency Register Values
  614
- Error Correction and Detection
  614
- ECC Write Flow
  615
- Ecc Generation
  615
- IXP45X/IXP46X Product Line G-Matrix (Generates the ECC)
  617
- Ecc Generation for Partial Writes
  617
- Sub 64-Bit DDRI SDRAM Write
  619
- Ecc Checking
  620
  - ECC Read Data Flow
    621
  - Developer's Manual August
    622
- Ecc Disabled
  625
- Ecc Testing
  625
- Overlapping Memory Regions
  626
- Ddri Sdram Clocking
  626
- MCU Error Response
  627
- Power Failure Mode
  627
- Interrupts/Error Conditions
  627
- Single-Bit Error Detection
  628
- Multi-Bit Error Detection
  629
- Memory Controller Register Table
  630
- Register Legend
  630
- DDRI SDRAM Initialization Register SDIR
  632
- DDRI SDRAM Control Register 0 SDCR0
  633
- DDRI SDRAM Control Register 1 SDCR1
  635
- DDRI SDRAM Base Register SDBR
  637
- DDRI SDRAM Boundary Register 0 SBR0
  638
- DDRI SDRAM Boundary Register 1 SBR1
  639
- ECC Control Register ECCR
  640
- ECC Log Registers ELOG0, ELOG1
  641
- ECC Address Registers ECAR0, ECAR1
  642
- ECC Test Register ECTST
  643
- Memory Controller Interrupt Status Register MCISR
  644
- MCU Port Transaction Count Register MPTCR
  645
- MCU Preemption Control Register MPCR
  645
- Refresh Frequency Register RFR
  646
- SDRAM Page Registers SDPR0-7
  647
- Expansion Bus Controller
  649
- Outbound Transfers
  650
- August
  650
- Expansion Bus Controller
  650
- Supported AHB Commands
  652
- Trimmed Version of IXP45X/IXP46X Network Processors Memory Map
  653
- Expansion Bus Address Space
  653
- Chip Select Address Allocation
  653
- Chip Select Address Allocation When There Are no 32-Mbyte Devices Programmed
  654
- Expansion Bus Memory Sizing
  654
- Chip Select Address Allocation When a 32-Mbyte Device Is Programmed
  655
- Address and Data Byte Steering
  655
- Expansion Bus Address and Data Byte Steering
  656
- Expansion Bus Interface Configuration
  658
- Using I/O Wait
  661
  - I/O Wait Normal Phase Timing
    662
  - I/O Wait Extended Phase Timing
    663
- August
  663
- Special Design Knowledge for Using HPI Mode
  664
- Multiplexed Output Pins for HPI Operation
  664
- Expansion Bus Outbound Timing Diagrams
  665
- HPI HCNTL Control Signal Decoding
  665
- Expansion Bus Write (Intel, Multiplexed Mode)
  666
- Expansion Bus Read (Intel, Multiplexed Mode)
  667
- Expansion Bus Write (Intel Simplex-Mode, Synchronous Intel)
  668
- Expansion Bus Read (Intel Simplex-Mode)
  669
- Intel Synchronous 8-Word Read
  670
- Intel Synchronous One-Word Read
  671
- Micron* ZBT Write/Read/Write
  672
- Micron* ZBT 8-Word Read
  673
- Micron* ZBT 4-Word Write
  674
- Expansion Bus Write (Motorola*, Multiplexed Mode)
  675
- Expansion Bus Read (Motorola*, Multiplexed Mode)
  676
- Expansion Bus Write (Motorola*, Simplex Mode)
  677
- Expansion Bus Read (Motorola*, Simplex Mode)
  678
- Expansion Bus Write (TI* HPI-8 Mode)
  679
- Expansion Bus Read (TI* HPI-8 Mode)
  679
- Expansion Bus Write (TI* HPI-16, Multiplexed Mode)
  680
- Expansion Bus Read (TI* HPI-16, Multiplexed Mode)
  680
- Expansion Bus Write (TI* HPI-16, Simplex Mode)
  681
- Expansion Bus Read (TI* HPI-16, Simplex Mode)
  681
- Inbound Transfers
  681
- Supported Inbound Expansion Bus Transfers
  682
- Expansion Bus Inbound State Diagram
  685
- Internal Arbitration
  687
- External Arbiter
  688
- Multiple Processors Connected by the Expansion Bus
  688
- Multiple IXP45X/IXP46X Network Processors Connected Back-To-Back
  689
- Expansion Bus Inbound Timing Diagrams
  690
- Back-To-Back 1-Word Writes Without Deasserting EX_SLAVE_CS_N
  691
- Eight-Word Inbound Write with Master Wait States
  692
- Eight-Word Inbound Write
  693
- Eight-Word Inbound Write with NOPS
  693
- Eight-Word Inbound Write with EX_SLAVE_CS_N Deassertion
  694
- Back-To-Back 1-Word Inbound Reads with EX_SLAVE_CS_N
  695
- Back-To-Back 1-Word Reads Without EX_SLAVE_CS_N Deasserted
  696
- Eight-Word Inbound Read
  696
- Eight-Word Inbound Read with Master Wait States
  697
- Eight-Word Inbound Read with Deassertion of EX_SLAVE_CS_N
  698
- Expansion Bus Arbiter Timing Diagrams
  698
- Arbitration When Grantremove Bit in EXP_MST_CONTROL Is Set
  698
- Arbitration When Grantremove Bit in EXP_MST_CONTROL Is Clear
  699
- External Expansion Bus Timing Diagram
  700
- External Arbiter Timing Diagram
  700
- Configuration Straps
  700
- Sampling EX_ADDR During Reset
  701
- Detailed Register Descriptions
  701
- Register Legend
  701
- Expansion Bus Controller Operation
  701
- Register Legend
  702
  - Legacy Expansion Bus Register Summary
    702
  - Non-Legacy Expansion Bus Register Summary
    702
- Timing and Control Registers for Chip Select 0
  703
- Timing and Control Registers for Chip Select 1
  703
- Timing and Control Registers for Chip Select 2
  703
- Timing and Control Registers for Chip Select 3
  704
- Timing and Control Registers for Chip Select 4
  704
- Timing and Control Registers for Chip Select 5
  704
- Timing and Control Registers for Chip Select 6
  705
- Timing and Control Registers for Chip Select 7
  705
- Bit Level Definition for each of the Timing and Control Registers
  705
- Configuration Register 0
  706
- EX_ADDR Operation
  707
- Configuration Register 0 Description
  707
- Processor Operation Speed
  709
- Configuration Register 1
  709
- Expansion Bus Configuration Register 1-Bit Definition
  710
- Exp_Unit_Fuse_Reset
  713
- Exp_Smiidll
  716
- Exp_Mst_Control
  716
- EX_ADDR Value to Access EXP_INBOUND_ADDR Register
  719
- Exp_Lock1
  720
- EX_ADDR Value to Access EXP_LOCK0 Register
  720
- Exp_Parity_Status
  721
- EX_ADDR Value to Access EXP_LOCK1 Register
  721
- Exp_Syncintel_Count
  722
- HSS Coprocessor
  723
- Overview
  723
- High-Speed Serial Interface Receive Operation
  724
- High-Speed Serial Interface Transmit Operation
  725
- Theory of Operation
  726
- Fifos and Lookup Tables
  727
  - Look-Up Table Organization
    728
  - HSS Core RX Buffer Structure (Identical to TX Buffer Structure)
    729
- Endianness
  730
- Programmable Frame Pulse Offset and Frame Synchronization
  730
- Underflow/Overflow/Unexpected Frame Pulse
  732
- Frameless Data Protocol Support
  733
- Loopback
  733
- K Mode
  733
- HSS Registers and Clock Configuration
  734
- HSS Clock and Jitter
  734
- Overview of HSS Clock Configuration
  735
- HSS Tx/Rx Clock Output
  735
- HSS Tx/Rx Clock Output Frequencies and PPM Error
  735
- HSS Tx/Rx Clock Output Frequencies and Associated Jitter Characterization
  735
- Jitter Definitions
  736
- Hss Supported Framing Protocols
  736
- Line-Card Mode
  740
- GCI Frames, Internally Generated Frame Pulse (Line-Card Mode)
  741
- Timeslot Configurations
  741
- August
  741
- Termination Mode
  741
- Mvip
  742
- GCI Frames, Internally Generated Frame Pulse (Termination Mode)
  742
  - MVIP, Interleaved Mapping of a T1 Frame to an E1 Frame
    743
  - MVIP, Frame Mapping a T1 Frame to an E1 Frame
    744
- MVIP, Byte Interlacing Two E1 Streams Onto a 4.096-Mbps Backplane
  745
- MVIP, Byte Interleaving Two T1 Streams Onto a 4.096-Mbps Backplane
  746
- MVIP, Byte Interleaving Four E1 Streams Onto a 8.192-Mbps Backplane Bus
  746
- Developer's Manual August
  748
- Universal Asynchronous Receiver-Transmitter (UART)
  749
- UART Timing Diagram
  750
- Block Diagram
  751
- Setting the Baud Rate
  753
- Setting Data Bits/Stop Bits/Parity
  753
- Typical Baud-Rate Settings
  753
- UART Transmit Parity Operation
  755
- UART Receive Parity Operation
  755
- UART Word-Length Select Configuration
  755
- Using the Modem Control Signals
  756
- Uart Interrupts
  757
- Transmitting and Receiving Uart Data
  760
- UART FIFO Trigger Level
  761
- Register Legend
  761
- Interrupt Enable Register
  762
- Register Legend
  762
- Receive Buffer Register
  762
- UART Registers Overview
  762
- Transmit Holding Register
  763
- Divisor Latch Low Register
  763
- Divisor Latch High Register
  764
- Interrupt Identification Register
  765
- UART IDD Bit Mapping
  767
- Fifo Control Register
  767
- Line Control Register
  768
- Modem Control Register
  770
- Line Status Register
  771
- Modem Status Register
  772
- Scratch-Pad Register
  773
- Infrared Selection Register
  774
- August
  774
- GPIO Controller
  776
- Overview
  776
- Theory of Operation
  777
- Input Meta-Stability Protection, Edge Detect Logic, Pulse Discrimination
  778
- Clock Generation
  778
- Register Summary
  779
- Register Legend
  779
- GPIO Output Register
  779
- Detailed Register Descriptions
  779
- Apb Interface
  779
- GPIO Output Enable Register
  780
- GPIO Input Register
  781
- GPIO Interrupt Status Register
  781
- GPIO Interrupt Type Register 1
  782
- GPIO Interrupt Type Register 2
  783
- GPIO Clock Register
  784
  - Developer's Manual August
    786
  - Overview
    787
- Performance Monitoring Unit (Pmu)
  787
- Occurrence Events
  788
- Duration Events
  789
- Performance Monitoring
  791
- Halt: Performance Monitoring Disabled
  791
- Cycle Count
  791
- Mcu: Dram Transactions
  791
- Previous Master and Slave
  792
- Miscellaneous
  792
- Register Legend
  793
- PMU Register Table
  793
- Detailed Register Descriptions
  793
- Event Select Registers
  794
- PMU Status Register
  795
- PMU Mode Register
  795
- Programmable Event Counters
  796
- Previous Master/Slave Register
  797
- Event Mapping
  798
  - AHB North PMU Mapping
    798
  - Interrupt Controller
    803
  - Overview
    803
  - Intel Xscale Processor Interrupt Mapping
    804
  - Interrupt Controller Block Diagram
    806
  - Interrupt Priority
    807
  - Assigning FIQ or IRQ Interrupts
    808
  - Enabling and Disabling Interrupts
    809
  - Reading Interrupt Status
    809
  - Error Enable Register
    811
  - Interrupt Controller Memory Mapped Registers
    811
  - Interrupt Controller Register Descriptions
    811
  - Register Legend
    811
  - Interrupt Status Register
    812
  - Interrupt Select Register
    813
  - Fiq Status Register
    814
  - IRQ Status Register
    814
  - Interrupt Priority Register
    815
  - Irq Highest-Priority Register
    815
  - Error High Priority Enable Register
    816
  - Fiq Highest-Priority Register
    816
  - Operating System Timer
    817
  - Operating System Timer Block Diagram
    818
  - Watchdog Timer Operation
    818
  - Timestamp Timer Operation
    819
  - General-Purpose Timers Operation
    820
  - Clock Prescale
    821
  - Register Summary
    821
  - General-Purpose Timer 0
    822
  - Register Summary
    822
  - Timestamp Timer
    822
  - General-Purpose Timer 0 Reload
    823
  - General-Purpose Timer 1
    823
  - General-Purpose Timer 1 Reload
    824
  - Watchdog Timer
    824
  - Watchdog Enable Register
    825
  - Watchdog Key Register
    825
  - Timer Status
    826
  - Timestamp Compare Register
    826
  - Timestamp Configuration Register
    827
  - Timestamp Prescale Register
    827
  - General-Purpose Timer 0 Configuration Register
    828
  - General-Purpose Timer 0 Prescale Register
    828
  - General-Purpose Timer 1 Configuration Register
    829
  - General-Purpose Timer 1 Prescale Register
    829
  - Time Synchronization Hardware Assist (Tsync)
    830
    
    Block Diagram of Tsync Circuit
    831
    
    Theory of Operation (Ethernet Interfaces)
    831
  - Follow_Up Message
    832
  - Priority Message Support
    832
  - Time Stamp Reference Point
    832
  - Ipv6 Compatibility
    833
  - MII Clocking Methods
    833
  - System Time Clock Rate Set by Addend Register
    833
  - Traffic Analyzer Support
    833
  - MII Message Detection
    834
    
    System Time Clock Rates
    834
    
    Errors in Messages
    835
  - Master Mode Programming Considerations
    836
  - Register Legend
    836
  - Register Map
    836
  - Slave Mode Programming Considerations
    836
  - Theory of Operation (Auxiliary Snapshots)
    836
  - Register Summary Table
    837
    
    August
    838
    
    Register Descriptions
    838
  - Register Summary
    838
  - Time Sync Control Register
    839
  - Addend Register
    840
  - Time Sync Event Register
    840
  - Accumulator Register
    841
  - Test Register
    842
  - Rawsystemtime_High Register
    843
  - Rawsystemtime_Low Register
    843
  - Systemtime_High Register
    844
  - Systemtime_Low Register
    844
  - Targettime_High Register
    845
  - Targettime_Low Register
    845
  - Auxiliary Slave Mode Snapshot High Register – Asms_High
    846
  - Auxiliary Slave Mode Snapshot Low Register – Asms_Low
    846
  - Auxiliary Master Mode Snapshot High Register – Amms_High
    847
  - Auxiliary Master Mode Snapshot Low Register – Amms_Low
    847
  - Ts_Channel_Control Register (Per Channel)
    848
  - Ts_Channel_Event Register (Per Channel)
    849
  - Xmit_Snapshot_Low Register (Per Channel)
    850
  - Xmit_Snapshot_High Register (Per Channel)
    851
  - Recv_Snapshot Low Register (Per Channel)
    852
  - Recv_Snapshot High Register (Per Channel)
    853
  - Sourceuuid0_Low Register (Per Channel)
    854
  - Sequenceid/Sourceuuid_High Register (Per Channel)
    855
  - Developer's Manual August
    856
  - Processor-Initiated Data Transfer
    857
  - SSP Operation
    857
  - Synchronous Serial Port
    857
  - Data Formats
    858
  - Serial Data Formats for Transfer To/From Peripherals
    858
    
    Spi Format — Detail
    859
    
    Ssp Format — Detail
    859
  - Texas Instruments* Synchronous Serial Frame Format
    859
  - Microwire* Format — Details
    861
  - Motorola* SPI Frame Format
    861
  - Buffer Operation
    862
  - Parallel Data Formats for Buffer Storage
    862
  - Baud-Rate Generation
    863
  - SSP Serial Port Register Summary
    863
  - Data Size Select (Dss)
    864
  - External Clock Select (Ecs)
    864
  - Frame Format (Frf)
    864
  - Ssp Control Register 0 (Sscr)
    864
  - Synchronous Serial Port Enable (Sse)
    864
  - Serial Clock Rate (Scr)
    865
  - Loop Back Mode (Lbm)
    866
  - Receive Fifo Interrupt Enable (Rie)
    866
  - Ssp Control Register 1 (Sscr)
    866
  - Transmit Fifo Interrupt Enable (Tie)
    866
  - Motorola* SPI Frame Formats for SPO and SPH Programming
    867
  - Serial Clock Phase (Sph)
    867
  - Serial Clock Polarity (Spo)
    867
  - Enable Fifo Write/Read Function (Efwr)
    868
  - National Microwire* Data Size (Mwds)
    868
  - Receive Fifo Interrupt Threshold (Rft)
    868
  - Select Fifo for Enable Fifo Write/Read (Strf)
    868
  - Transmit Fifo Interrupt Threshold (Tft)
    868
  - SSP Status Register
    869
  - Receive Fifo Not Empty Flag (Rne) (Read-Only, Non-Interruptible)
    870
  - Receive FIFO Service Request Flag (RFS) (Read-Only, Maskable Interrupt)
    870
  - Receiver Overrun Status (Ror)
    870
  - Ssp Busy Flag (Bsy) (Read-Only, Non-Interruptible)
    870
  - Transmit Fifo Not Full Flag (Tnf) (Read-Only, Non-Interruptible)
    870
  - Transmit FIFO Service Request Flag (TFS) (Read-Only, Maskable Interrupt)
    870
  - Receive Fifo Level (Rfl)
    871
  - Transmit Fifo Level (Tfl)
    871
  - Ssp Data Register (Ssdr)
    872
  - Ssp Interrupt Test Register (Ssitr)
    872
  - Developer's Manual August
    874
  - I2C Bus Interface Unit
    875
  - Overview
    875
  - C Bus Definitions
    876
  - C Bus Interface Unit Block Diagram
    876
  - C Bus Configuration Example
    877
  - Operational Blocks
    877
  - Modes of Operation
    878
  - START and STOP Bit Definitions
    879
  - Start and Stop Bus States
    879
  - No Start or Stop Condition
    880
  - START and STOP Conditions
    880
  - Start Condition
    880
  - Serial Clock Line (SCL) Generation
    881
  - START and STOP Condition Events
    881
  - STOP Condition
    881
  - Addressing a Slave Device
    882
  - Data and Addressing Management
    882
    
    I 2 C Acknowledge
    882
    
    Data Format of First Byte in Master Transaction
    883
  - Acknowledge on the I
    884
  - Arbitration
    884
  - Scl Arbitration
    884
  - Arbitration Procedure of Two Masters
    885
  - Clock Synchronization During the Arbitration Procedure
    885
  - Sda Arbitration
    885
  - Master Operations
    886
  - I 2 C Bus Operation
    887
  - Master Transactions
    887
  - Master-Receiver Read from Slave-Transmitter
    888
  - A Complete Data Transfer
    889
  - Master-Receiver Read from Slave-Transmitter / Repeated Start
    889
  - Master-Transmitter Write to Slave-Receiver
    889
  - Slave Operations
    889
  - Master-Receiver Read to Slave-Transmitter
    891
  - Master-Receiver Read to Slave-Transmitter, Repeated START
    891
  - Master-Transmitter Write to Slave-Receiver
    891
  - General Call Address
    892
  - General Call Address Second Byte Definitions
    892
  - Slave Mode Programming Examples
    892
  - Write N Bytes as a Slave
    892
  - Read N Bytes as a Slave
    893
  - Master Programming Examples
    894
  - Read 1 Byte as a Master
    894
  - Write 1 Byte as a Master
    894
  - Read 2 Bytes as a Master — Send Stop Using the Abort
    895
  - Write 2 Bytes and Repeated Start Read 1 Byte as a Master
    895
  - Glitch Suppression Logic
    896
  - C Control Register - ICR
    897
  - C Register Addresses
    897
    
    I 2 C Bus Monitor Register - IBMR
    897
    
    I 2 C Data Buffer Register - IDBR
    897
    
    I 2 C Slave Address Register - ISAR
    897
    
    I 2 C Status Register - ISR
    897
  - Public Key Exchange Crypto Engine
    905
  - AHB-PKE Bridge
    907
  - August
    907
  - Overview
    907
    
    AHB-PKE Bridge Block Diagram
    908
    
    Peripheral Information
    908
  - PKE Peripheral Memory Map and Access Information
    908
  - Random Number Generator
    911
    
    Register Legend
    911
    
    Register Summary
    911
  - Theory of Operation
    911
  - Power-Management Requirements
    912
  - Random Number FIFO
    912
  - Exponentiation Acceleration Unit
    913
  - EAU Operand Size Restrictions and Assumptions
    914
  - Exponentiation Acceleration Unit: Block Diagram
    914
  - Operand Restrictions
    914
  - Detailed Register Descriptions
    915
  - EAU Command Register
    915
  - Eau Ram Reads
    915
  - Eau Ram Writes
    915
  - Eau Count Register
    917
  - Eau Status Register
    917
  - EAU Interrupt Register
    918
  - Eau Ram Registers
    918
  - Performance Requirements
    919
  - Block Diagram
    921
  - Detailed Register Descriptions
    921
  - Hashing Coprocessor: Register Summary
    921
  - Hashing Unit (Sha)
    921
  - Hash Configuration Register
    922
  - Hash Do Register
    922
  - Hash Chain Register
    923
  - Hash Interrupt Register
    923
  - Hash Data Fifo
    924
  - Ahb Queue Manager (Aqm)
    926
  - Overview
    926
  - AHB Queue Manager
    927
  - Ahb Interface
    928
  - AHB Queue Manager Memory Map
    928
  - Queue Control
    929
  - Representative Logical Diagram of a Queue
    931
  - Queue Status
    933
  - Status Update
    933
  - Queue Status Flags
    934
  - Status Interrupts
    934
  - Aqm Sram
    935
  - Data Validity Cases and Their Handling
    936
  - Burst Operations to Queues
    937
    
    Queue Access Word Registers 0 - 63
    939
    
    Queues 0-31 Status Register 0 - 3
    939
  - Queues 32-63 Empty Status Register
    940
    
    Underflow/Overflow Status Register 0 - 1
    940
    
    Memory Controller Unit (Mcu), Multiple-Bit, Ecc Error
    951
  - NPE Coprocessor Error
    953
    
    NPE Error Handling Illustration
    953
    
    Expansion Bus Controller Response to Errors
    957
    
    Developer's Manual August
    958

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