Start And Stop Bus States; Start And Stop Bit Definitions - Intel IXP45X Developer's Manual

I2C Bus Interface Unit—Intel
When the I
found in the I
interface will either remain in Slave-Receive mode or transition to Slave-Transmit
mode. This is determined by the Read/Write (R/W#) bit (the least significant bit of the
byte containing the slave address). If the
R/W# bit is low, the master initiating the transaction intends to do a write and the I
Bus Interface Unit will remain in Slave-Receive mode. If the R/W# is high, the initiating
master wants to read data and the slave transitions to Slave-Transmit mode. Slave
operation is further defined in
When the IXP45X/IXP46X network processors want to initiate a read or write on the I
bus, the I
Master-Transmit mode. If the processor wants to write data, the interface remains in
Master-Transmit mode after the address transfer has completed. (see
Condition" on page
2
the I C Bus Interface Unit will transmit the start address, then transition to Master-
Receive mode. Master operation is further defined in
21.4.3

Start and Stop Bus States

2
The I C bus defines a transaction START and a transaction STOP bus state that are
used at the beginning and end of the transfer of one to an unlimited number of bytes
on the bus.
The IXP45X/IXP46X network processors use the START and STOP bits in the I
Register (ICR) to:
• Initiate an additional byte transfer
• Initiate a START condition on the I
• Enable Data Chaining (repeated START)
• Initiate a STOP condition on the I
Table 278
Table 278.

START and STOP Bit Definitions

STOP START
Bit
0
0
1
Figure 192
STOP condition.
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
2
C Bus Interface Unit receives an address that matches the 7-bit address
2
C Slave Address Register (ISAR) or the General Call Address (00H), the
2
C Bus Interface Unit will transition from the default Slave-Receive mode to
880) for START information). If the processor wants to read data,
summarizes the definition of the START and STOP bits in the ICR.
Condition
Bit
No START or No START or STOP condition is sent by the I
0
STOP used when multiple data bytes need to be transferred.
The I
contents of the 8 bit IDBR after the START. The IDBR must contain the 7-bit
address and the R/W# bit before a START is initiated.
START Condition
For a repeated start, the IDBR contents will contain the target slave address
and
1
and the R/W# bit. This enables multiple transfers to different slaves without
Repeated START
giving up the bus.
The interface will stay in Master-Transmit mode if a write is used or
transition to master-receive mode if a read is requested.
In Master-Transmit mode, the I
IDBR and then send a STOP on the I
In Master-Receive mode, the Ack/Nack Control bit in the ICR must be
X STOP Condition
changed to a negative Ack (see
will write the Nack bit (Ack/Nack Control bit must be 1), receive the data
byte in the IDBR, then send a STOP on the I
shows the relationship between the SDA and SCL lines for a START and
"Slave Operations" on page
2
C bus
2
C bus
2
C Bus Interface Unit will send a START condition and transmit the
2
C Bus Interface Unit will transmit the 8-bit
Section
® ®
Intel IXP45X and Intel
889.
"START
"Master Operations" on page
Notes
2
C Bus Interface Unit. This is
2
C bus.
2
21.5.3). The I C Bus Interface Unit
2
C bus.
IXP46X Product Line of Network Processors
Developer's Manual
2
C
2
C
886.
2
C Control
879