Register Description; Clock Counter (Ccnt); Performance Count Registers; Clock Count Register (Ccnt) - Intel IXP45X Developer's Manual

Intel
3.7.2

Register Description

Table 56.

Register Legend

Attribute
RV
PR
RS
RW
RW1C
3.7.2.1

Clock Counter (CCNT)

The format of CCNT is shown in
2 in the Performance Monitor Control Register (PMNC) or can be set to a predetermined
value by directly writing to it. It counts core clock cycles. When CCNT reaches its
maximum value 0xFFFF,FFFF, the next clock cycle will cause it to roll over to zero and
set the overflow flag (bit 0) in FLAG. An interrupt request will occur if it is enabled via
bit 0 in INTEN.
Table 57.

Clock Count Register (CCNT)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: unpredictable
Bits
31:0
3.7.2.2

Performance Count Registers

There are four 32-bit event counters; their format is shown in
counters are reset to '0' by setting bit 1 in the PMNC register or can be set to a
predetermined value by directly writing to them. When an event counter reaches its
maximum value 0xFFFF,FFFF, the next event it needs to count will cause it to roll over
to zero and set its corresponding overflow flag (bit 1,2,3 or 4) in FLAG. An interrupt
request will be generated if its corresponding interrupt enable (bit 1,2,3 or 4) is set in
INTEN.
Table 58.

Performance Monitor Count Register (PMN0 - PMN3)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: unpredictable
Bits
31:0
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
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IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale
Legend
Reserved
Preserved
Read/Set
Read/Write
Normal Read
Write '1' to clear
Access
Read / Write
Access
Read / Write
Attribute Legend
RC Read Clear
RO Read Only
WO Write Only
NA Not Accessible
Normal Read
RW1S
Write '1' to set
Table 57. The clock counter is reset to '0' by setting bit
Clock Counter
32-bit clock counter - Reset to '0' by PMNC register.
When the clock counter reaches its maximum value
0xFFFF,FFFF, the next cycle will cause it to roll over to
zero and generate an interrupt request if enabled.
Event Counter
32-bit event counter - Reset to '0' by PMNC register.
When an event counter reaches its maximum value
0xFFFF,FFFF, the next event it needs to count will cause it
to roll over to zero and generate an interrupt request if
enabled.
®
Processor
8 7 6 5 4 3 2
Description
Table 58. The event
8 7 6 5 4 3 2
Description
August 2006
Order Number: 306262-004US
1 0
1 0