Udc Status/Interrupt Register 0; Endpoint 0 Interrupt Request (Ir0) - Intel IXP45X Developer's Manual

Bits
31:8
7
6
5
4
3
2
1
0
8.5.20

UDC Status/Interrupt Register 0

The UDC status/interrupt registers (USIR0 and USIR1) contain bits that are used to
generate the UDC's interrupt request. Each bit in the UDC status/interrupt registers is
logically ORed together to produce one interrupt request.
When the ISR for the UDC is executed, it must read the UDC status/interrupt register
to determine why the interrupt occurred.
The bits in USIR0 and USIR1 are controlled by a mask bit in the UDC Interrupt Control
Register (UICR0/1). The mask bits, when set, prevent a status bit in the USIRx from
being set. If the mask bit for a particular status bit is cleared and an interruptible
condition occurs, the status bit is set.
To clear status bits, the Intel XScale processor must write a 1 to the position to be
cleared. The interrupt request for the UDC remains active as long as the value of the
USIRx is non-zero.
8.5.20.1

Endpoint 0 Interrupt Request (IR0)

The endpoint 0 interrupt request is set if the IM0 bit in the UDC control register is
cleared and, in the UDC endpoint 0 control/status register, the OUT packet ready bit is
set, the IN packet ready bit is cleared, or the sent STALL bit is set. The IR0 bit is
cleared by writing a 1 to it.
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
330
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Intel IXP45X and Intel
Register
Name
Reserved for future use.
Interrupt mask for Endpoint 15.
IM15 0 = Transmit interrupt enabled.
1= Transmit interrupt disabled.
Interrupt mask for Endpoint 14.
IM14 0 = Receive interrupt enabled.
1 = Receive interrupt disabled.
Interrupt mask for Endpoint 13.
IM13 0 = Transmit interrupt enabled.
1 = Transmit interrupt disabled.
Interrupt mask for Endpoint 12.
IM12 0 = Receive interrupt enabled.
1 = Receive interrupt disabled.
Interrupt mask for Endpoint 11.
IM11 0 = Transmit interrupt enabled.
1 = Transmit interrupt disabled.
Interrupt mask for Endpoint 10.
IM10 0 = Receive interrupt enabled.
1 = Receive interrupt disabled.
Interrupt mask for Endpoint 9.
IM9 0 = Receive interrupt enabled.
1 = Receive interrupt disabled.
Interrupt Mask for Endpoint 8.
IM8 0 = Transmit interrupt enabled.
1 = Transmit interrupt disabled.
IXP46X Product Line of Network Processors—USB 1.1 Device
UICR1
Description
Controller
(UISR0)
August 2006
Order Number: 306262-004US