Overview; Performance Monitoring Unit (Pmu) - Intel IXP45X Developer's Manual

Performance Monitoring Unit (PMU)—Intel
Processors
16.0

Performance Monitoring Unit (PMU)

16.1

Overview

This chapter describes the components which comprise the Performance Monitoring
Unit (PMU). These features aid in measuring and monitoring various system
parameters that contribute to the overall performance of the Intel
IXP46X Product Line of Network Processors. Operation modes, setup mechanisms,
registers, and interrupts are also described in this chapter.
The Performance Monitoring (PMON) facility provided by the PMU comprises:
• Eight Programmable Event Counters (PECx)
• Previous Master/Slave Register
• Event-selection mux
The programmable event counters are 27 bits wide. Each counter may be programmed
to observe one event from a defined set of events. An event consists of a set of
parameters which define a condition. The monitored events are selected by
programming the Event Select Registers (ESRx).
The PMU is inherently a model specific function. This definition attempts to make the
design and software model of the PMU more regular. However, the definition of events
between instantiations of the PMU on various members of the family of network
processors can be expected to change. However this specification makes access to
these events highly regular and allows a simple table driven approach to associating
the programming to event specification mapping.
There is lots of empty space in the event address map which will enable future
expansion.
16.2 Feature List
The major features of the PMU are:
• Eight Programmable Event Count Registers
• Duration and Event detection logic
• Monitoring mechanisms
• Event selection logic
• Previous accessing/accessed Master/ Slave Register
16.3 Functional Description
The PMU comprises:
• Eight Programmable Event Counters (PEC).
• Event Selection logic
August 2006
Order Number: 306262-004US
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