Intel IXP45X Developer's Manual page 902

Intel
2
21.10.4 I C Data Buffer Register - IDBR
2
The I C Data Buffer Register is used by the IXP45X/IXP46X network processors to
transmit and receive data from the I
IXP46X network processors on one side and by the I
coming into the I
been received and acknowledged. Data going out of the I
written to the IDBR by the processor core and sent to the serial bus.
When the I
writes data to the IDBR over the internal bus. This occurs when a master transaction is
initiated or when the IDBR Transmit Empty Interrupt is signalled. Data is moved from
the IDBR to the shift register when the Transfer Byte bit is set. The IDBR Transmit
Empty Interrupt will be signalled (if enabled) when a byte has been transferred on the
2
I C bus and the acknowledge cycle is complete. If the IDBR is not written by the
processor (and a STOP condition was not in place) before the I
transfer the next byte packet, the I
processor writes the IDBR and sets the Transfer Byte bit.
When the I
IXP46X network processors will read IDBR data over the internal bus. This occurs when
the IDBR Receive Full Interrupt is signalled. The data is moved from the shift register to
the IDBR when the Ack cycle is complete. The I
states until the IDBR has been read. Refer to
page 883
reads the IDBR, the Ack/Nack Control bit is written and the Transfer Byte bit is written,
allowing the next byte transfer to proceed on the I
after reset.
Register Name:
Block
0xC801_100C
Base Address:
2
I C Data Buffer Register - IDBR
Register Description:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Register
Bits Name
31:0
— (Reserved)
8
2
I C Data
7:0 Buffer for I
Buffer
2
21.10.5 I C Bus Monitor Register - IBMR
2
The I C Bus Monitor Register (IBMR) tracks the status of the SCL and SDA pins. The
values of these pins are recorded in this read-only register so that software may
determine if the I
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
902
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—I2C Bus Interface Unit
2
C Bus Interface Unit is received into the IDBR after a full byte has
2
C Bus Interface Unit is in transmit mode (master or slave), the processor
2
C Bus Interface Unit is in receive mode (master or slave), the IXP45X/
for acknowledge pulse information in receiver mode. After the processor
I
Offset Address
(Reserved)
Description
2
C bus send/receive data.
2
C bus is hung and the I
2
C bus. The IDBR is accessed by the IXP45X/
2
C shift register on the other. Data
2
C Bus Interface Unit will insert wait states until the
2
C Bus Interface Unit will insert wait
Section 21.5.3, "I2C Acknowledge" on
2
C Bus. The IDBR register is 00H
2
C Data Buffer Register - IDBR
Reg
OffsetAddress
2
I C Data Buffer Register - IDBR
2
C unit must be reset.
2
C Bus Interface Unit is
2
C bus is ready to
0x0000_0000
Reset Value
Access: (See below.)
8 7 6 5 4 3 2
See table below.
Reset
Access
Value
000000H —
00H RW
August 2006
Order Number: 306262-004US
1 0