Arbitration Signals; Interrupt Signal; System Signals; Error Reporting Signals - Intel 82540EP Datasheet

3.2.2

Arbitration Signals

Symbol
REQ#
GNT#
LOCK#
3.2.3

Interrupt Signal

Symbol
INTA#
3.2.4

System Signals

Symbol
CLK
M66EN
RST#
CLKRUN#
3.2.5

Error Reporting Signals

Symbol
SERR#
PERR#
Datasheet
Type
Request Bus. The Request Bus signal is used to request control of the bus from the
TS
arbiter. This signal is point-to-point.
Grant Bus. The Grant Bus signal notifies the 82540EP that bus access has been
I
granted. This is a point-to-point signal.
Lock Bus. The Lock Bus signal is asserted by an initiator to require sole access to a
I target memory device during two or more separate transfers. The 82540EP device
does not implement bus locking.
Type
Interrupt A. Interrupt A is used to request an interrupt by port 1 of the 82540EP. It is an
TS
active low, level-triggered interrupt signal.
Type
PCI Clock.
T h e P C I C l o c k s i g n a l p r o v i d e s t i m i n g f o r a l l t r a n s a c t i o n s o n t h e P C I b u s a n d
82540EP
i s a n i n p u t t o t h e
I
( I N T A # ) a n d P C I R e s e t s i g n a l ( R S T # ) , a r e s a m p l e d o n t h e r i s i n g e d g e o f C L K . A l l o t h e r
t i m i n g p a r a m e t e r s a r e d e f i n e d w i t h r e s p e c t t o t h i s e d g e .
I 66 MHz Enable. M66EN indicates whether the system bus is enabled for 66MHz.
PCI Reset. When the PCI Reset signal is asserted, all PCI output signals, except the
Power Management Event signal (PME#), are floated and all input signals are ignored.
The PME# context is preserved, depending on power management settings.
I
Most of the internal state of the 82540EP is reset on the de-assertion (rising edge) of
RST#.
Clock Run. This signal is used by the system to pause the PCI clock signal. It is used
I/O
by the 82540EP controller to request the PCI clock. When the CLKRUN# feature is
OD
disabled, leave this pin unconnected.
Type
System Error. The System Error signal is used by the 82540EP controller to report
OD address parity errors. SERR# is open drain and is actively driven for a single PCI clock
when reporting the error.
Parity Error. The Parity Error signal is used by the 82540EP controller to report data
parity errors during all PCI transactions except by a Special Cycle. PERR# is sustained
STS tri-state and must be driven active by the 82540EP controller two data clocks after a
data parity error is detected. The minimum duration of PERR# is one clock for each
data phase a data parity error is present.
Networking Silicon — 82540EP
Name and Function
Name and Function
Name and Function
d e v i c e . A l l o t h e r P C I s i g n a l s , e x c e p t t h e I n t e r r u p t A
Name and Function
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