Operating System Timer - Intel IXP45X Developer's Manual

Operating System Timer—Intel
18.0

Operating System Timer

18.1 Overview
The OST serves the function of a watchdog timer as well as a general-purpose timer
and is capable of generating interrupts at predetermined intervals. The module
contains several registers which are written and read via the APB interface. All four
timers can generate interrupts, that can be independently cleared.
All timers in the OST run off the AMBA APB clock by default. An additional feature to the
OST makes it possible for each timer to use a prescaled clock. The timers may also
enable a 3/4 scaler to allow the emulation of a 50-MHz clock from a APB 66.667-MHz
input clock. All accesses to the OST are 32 bits (word) wide. Bits that correspond to
reserved register bits are ignored on "writes." These same bits will return zero on
"reads."
18.2 Feature List
• Two readable decrementing general-purpose timers with read/writable reload
registers (each suitable for use as an OS timer)
• 32-bit timestamp incrementing timer, with timestamp compare register.
• 32-bit watchdog timer (decrementing)
• Interrupt, reset enable, and watchdog count for watchdog timer
• "Key" protected access to watch dog register
• A 1-bit, warm-reset register that signifies when a warm reset has occurred from
this unit
• Peripheral on the AMBA APB
• Each timer except the watchdog timer can enable a 16-bit Prescaler.
• Each timer except the watchdog can enable a 3/4 scale function (to emulate a
20-ns clock [50 MHz] off a 66.66667-MHz clock).
• Separate configuration registers for each of the timers.
• The timestamp timer and the two general-purpose counters can be paused only if
the prescaler or the 3/4 scale function on the respective timer is enabled.
• Compatible with Intel
18.3 Block Diagram
A block diagram of the OST unit is shown in
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
®
IXP400 Software.
Intel
Figure 187.
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
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