Burst Operations To Queues - Intel IXP45X Developer's Manual

AHB Queue Manager (AQM)—Intel
Processors
On the overflow condition, the written data is permanently lost. On the underflow
condition, the data returned is zero.
If there are parity errors where the parity notification is not enabled, the data returned
represents the data containing the parity error. If parity notification is enabled and the
entry contains a parity error, the error is signaled on that particular bus cycle and
consistent with the AHB specification, the master has the option of terminating a burst
operation on the first error.
In general, a software usage model should treat the return of zero data as a suspicious
case and the data type stored in the AQM should take this into account. If the data type
were to be memory address pointers, this is well behaved since a null pointer is not
defined. Other data types should take this into account.
27.4.5

Burst Operations to Queues

Burst operations are useful for writing multiple entry queues. An INCR4 burst can fill an
entire entry for a four entry queue without having to re-arbitrate for ownership of the
AHB bus, which enhances performance. However, if the burst type does not match the
entry size for the queue, the transaction data to the inactive queue entries is simply
dropped. In general, software should avoid burst transactions to queues that have
fewer words per entry than the burst because of the decreased performance.
27.5 Detailed Register Descriptions
Table 296. Register Legend
Attribute
RV
PR
RS
RW
RW1C
*
Table 297. Register Summary (Sheet 1 of 2)
Address
0x60000000
0x60000004
0x60000008
0x6000000C
0x60000010
0x60000014
0x60000018
0x6000001C
August 2006
Reference Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network
Legend Attribute
Reserved RC
Preserved RO
Read/Set WO
Read/Write NA
Normal Read
RW1S
Write '1' to clear
Register Name
QUEACC0_0 Queue 0 word 0 data register
Queue 0 word 1 data register (used only when Queue 0
QUEACC0_1
has a entry size of 2 or 4)
Queue 0 word 2 data register (used only when Queue 0
QUEACC0_2
has a entry size of 4)
Queue 0 word 3 data register (used only when Queue 0
QUEACC0_3
has a entry size of 4)
QUEACC1_0 Queue 1 word 0 data register
Queue 1 word 1 data register (used only when Queue 1has
QUEACC1_1
a entry size of 2 or 4)
Queue 1 word 2 data register (used only when Queue 1has
QUEACC1_2
a entry size of 4)
Queue 1 word 3 data register (used only when Queue 1has
QUEACC1_3
a entry size of 4)
®
Intel IXP45X and Intel
Legend
Read Clear
Read Only
Write Only
Not Accessible
Normal Read
Write '1' to set
Description
®
IXP46X Product Line of Network Processors
Developer's Manual
Reset Value Access
N/A RW
N/A RW
N/A RW
N/A RW
N/A RW
N/A RW
N/A RW
N/A RW
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